include/asm-alpha/apecs.h

/* */
This source file includes following definitions.
virt_to_bus
bus_to_virt
__inb
__outb
__inw
__outw
__inl
__outl
__readb
__readw
__readl
__writeb
__writew
__writel
   1 #ifndef __ALPHA_APECS__H__
   2 #define __ALPHA_APECS__H__
   3 
   4 #include <linux/types.h>
   5 
   6 /*
   7  * APECS is the internal name for the 2107x chipset which provides
   8  * memory controller and PCI access for the 21064 chip based systems.
   9  *
  10  * This file is based on:
  11  *
  12  * DECchip 21071-AA and DECchip 21072-AA Core Logic Chipsets
  13  * Data Sheet
  14  *
  15  * EC-N0648-72
  16  *
  17  *
  18  * david.rusling@reo.mts.dec.com Initial Version.
  19  *
  20  */
  21 #include <linux/config.h>
  22 
  23 #ifdef CONFIG_ALPHA_XL
  24 /*
  25    An AVANTI *might* be an XL, and an XL has only 27 bits of ISA address
  26    that get passed through the PCI<->ISA bridge chip. So we've gotta use
  27    both windows to max out the physical memory we can DMA to. Sigh...
  28 
  29    If we try a window at 0 for 1GB as a work-around, we run into conflicts
  30    with ISA/PCI bus memory which can't be relocated, like VGA aperture and
  31    BIOS ROMs. So we must put the windows high enough to avoid these areas.
  32 
  33    We put window 1 at BUS 64Mb for 64Mb, mapping physical 0 to 64Mb-1,
  34    and window 2 at BUS 512Mb for 512Mb, mapping physical 0 to 512Mb-1.
  35    Yes, this does map 0 to 64Mb-1 twice, but only window 1 will actually
  36    be used for that range (via virt_to_bus()).
  37 
  38    Window 1 will be used for all DMA from the ISA bus; yes, that does
  39    limit what memory an ISA floppy or soundcard or Ethernet can touch, but
  40    it's also a known limitation on other platforms as well. We use the
  41    same technique that is used on INTEL platforms with similar limitation:
  42    set MAX_DMA_ADDRESS and clear some pages' DMAable flags during mem_init().
  43    We trust that any ISA bus device drivers will *always* ask for DMAable
  44    memory explicitly via kmalloc()/get_free_pages() flags arguments.
  45 
  46    Note that most PCI bus devices' drivers do *not* explicitly ask for
  47    DMAable memory; they count on being able to DMA to any memory they
  48    get from kmalloc()/get_free_pages(). They will also use window 1 for
  49    any physical memory accesses below 64Mb; the rest will be handled by
  50    window 2, maxing out at 512Mb of memory. I trust this is enough... :-)
  51 
  52    Finally, the reason we make window 2 start at 512Mb for 512Mb, is so that
  53    we can allocate PCI bus devices' memory starting at 1Gb and up, to ensure
  54    that no conflicts occur and bookkeeping is simplified (ie we don't
  55    try to fill the gap between the two windows, we just go above the top).
  56 
  57    Note that the XL is treated differently from the AVANTI, even though
  58    for most other things they are identical. It didn't seem reasonable to
  59    make the AVANTI support pay for the limitations of the XL. It is true,
  60    however, that an XL kernel will run on an AVANTI without problems.
  61 
  62 */
  63 #define APECS_XL_DMA_WIN1_BASE  (64*1024*1024)
  64 #define APECS_XL_DMA_WIN1_SIZE  (64*1024*1024)
  65 #define APECS_XL_DMA_WIN2_BASE  (512*1024*1024)
  66 #define APECS_XL_DMA_WIN2_SIZE  (512*1024*1024)
  67 
  68 #else /* CONFIG_ALPHA_XL */
  69 
  70 /* these are for normal APECS family machines, AVANTI/MUSTANG/EB64/PC64 */
  71 #define APECS_DMA_WIN_BASE      (1024*1024*1024)
  72 #define APECS_DMA_WIN_SIZE      (1024*1024*1024)
  73 
  74 #endif /* CONFIG_ALPHA_XL */
  75 
  76 /*
  77  * 21071-DA Control and Status registers.
  78  * These are used for PCI memory access.
  79  */
  80 #define APECS_IOC_DCSR                  (IDENT_ADDR + 0x1A0000000UL)
  81 #define APECS_IOC_PEAR                  (IDENT_ADDR + 0x1A0000020UL)
  82 #define APECS_IOC_SEAR                  (IDENT_ADDR + 0x1A0000040UL)
  83 #define APECS_IOC_DR1                   (IDENT_ADDR + 0x1A0000060UL)
  84 #define APECS_IOC_DR2                   (IDENT_ADDR + 0x1A0000080UL)
  85 #define APECS_IOC_DR3                   (IDENT_ADDR + 0x1A00000A0UL)
  86 
  87 #define APECS_IOC_TB1R                  (IDENT_ADDR + 0x1A00000C0UL)
  88 #define APECS_IOC_TB2R                  (IDENT_ADDR + 0x1A00000E0UL)
  89 
  90 #define APECS_IOC_PB1R                  (IDENT_ADDR + 0x1A0000100UL)
  91 #define APECS_IOC_PB2R                  (IDENT_ADDR + 0x1A0000120UL)
  92 
  93 #define APECS_IOC_PM1R                  (IDENT_ADDR + 0x1A0000140UL)
  94 #define APECS_IOC_PM2R                  (IDENT_ADDR + 0x1A0000160UL)
  95 
  96 #define APECS_IOC_HAXR0                 (IDENT_ADDR + 0x1A0000180UL)
  97 #define APECS_IOC_HAXR1                 (IDENT_ADDR + 0x1A00001A0UL)
  98 #define APECS_IOC_HAXR2                 (IDENT_ADDR + 0x1A00001C0UL)
  99 
 100 #define APECS_IOC_PMLT                  (IDENT_ADDR + 0x1A00001E0UL)
 101 
 102 #define APECS_IOC_TLBTAG0               (IDENT_ADDR + 0x1A0000200UL)
 103 #define APECS_IOC_TLBTAG1               (IDENT_ADDR + 0x1A0000220UL)
 104 #define APECS_IOC_TLBTAG2               (IDENT_ADDR + 0x1A0000240UL)
 105 #define APECS_IOC_TLBTAG3               (IDENT_ADDR + 0x1A0000260UL)
 106 #define APECS_IOC_TLBTAG4               (IDENT_ADDR + 0x1A0000280UL)
 107 #define APECS_IOC_TLBTAG5               (IDENT_ADDR + 0x1A00002A0UL)
 108 #define APECS_IOC_TLBTAG6               (IDENT_ADDR + 0x1A00002C0UL)
 109 #define APECS_IOC_TLBTAG7               (IDENT_ADDR + 0x1A00002E0UL)
 110 
 111 #define APECS_IOC_TLBDATA0              (IDENT_ADDR + 0x1A0000300UL)
 112 #define APECS_IOC_TLBDATA1              (IDENT_ADDR + 0x1A0000320UL)
 113 #define APECS_IOC_TLBDATA2              (IDENT_ADDR + 0x1A0000340UL)
 114 #define APECS_IOC_TLBDATA3              (IDENT_ADDR + 0x1A0000360UL)
 115 #define APECS_IOC_TLBDATA4              (IDENT_ADDR + 0x1A0000380UL)
 116 #define APECS_IOC_TLBDATA5              (IDENT_ADDR + 0x1A00003A0UL)
 117 #define APECS_IOC_TLBDATA6              (IDENT_ADDR + 0x1A00003C0UL)
 118 #define APECS_IOC_TLBDATA7              (IDENT_ADDR + 0x1A00003E0UL)
 119 
 120 #define APECS_IOC_TBIA                  (IDENT_ADDR + 0x1A0000400UL)
 121 
 122 
 123 /*
 124  * 21071-CA Control and Status registers.
 125  * These are used to program memory timing,
 126  *  configure memory and initialise the B-Cache.
 127  */
 128 #define APECS_MEM_GCR                   (IDENT_ADDR + 0x180000000UL)
 129 #define APECS_MEM_EDSR                  (IDENT_ADDR + 0x180000040UL)
 130 #define APECS_MEM_TAR                   (IDENT_ADDR + 0x180000060UL)
 131 #define APECS_MEM_ELAR                  (IDENT_ADDR + 0x180000080UL)
 132 #define APECS_MEM_EHAR                  (IDENT_ADDR + 0x1800000a0UL)
 133 #define APECS_MEM_SFT_RST               (IDENT_ADDR + 0x1800000c0UL)
 134 #define APECS_MEM_LDxLAR                (IDENT_ADDR + 0x1800000e0UL)
 135 #define APECS_MEM_LDxHAR                (IDENT_ADDR + 0x180000100UL)
 136 #define APECS_MEM_GTR                   (IDENT_ADDR + 0x180000200UL)
 137 #define APECS_MEM_RTR                   (IDENT_ADDR + 0x180000220UL)
 138 #define APECS_MEM_VFPR                  (IDENT_ADDR + 0x180000240UL)
 139 #define APECS_MEM_PDLDR                 (IDENT_ADDR + 0x180000260UL)
 140 #define APECS_MEM_PDhDR                 (IDENT_ADDR + 0x180000280UL)
 141 
 142 /* Bank x Base Address Register */
 143 #define APECS_MEM_B0BAR                 (IDENT_ADDR + 0x180000800UL)
 144 #define APECS_MEM_B1BAR                 (IDENT_ADDR + 0x180000820UL)
 145 #define APECS_MEM_B2BAR                 (IDENT_ADDR + 0x180000840UL)
 146 #define APECS_MEM_B3BAR                 (IDENT_ADDR + 0x180000860UL)
 147 #define APECS_MEM_B4BAR                 (IDENT_ADDR + 0x180000880UL)
 148 #define APECS_MEM_B5BAR                 (IDENT_ADDR + 0x1800008A0UL)
 149 #define APECS_MEM_B6BAR                 (IDENT_ADDR + 0x1800008C0UL)
 150 #define APECS_MEM_B7BAR                 (IDENT_ADDR + 0x1800008E0UL)
 151 #define APECS_MEM_B8BAR                 (IDENT_ADDR + 0x180000900UL)
 152 
 153 /* Bank x Configuration Register */
 154 #define APECS_MEM_B0BCR                 (IDENT_ADDR + 0x180000A00UL)
 155 #define APECS_MEM_B1BCR                 (IDENT_ADDR + 0x180000A20UL)
 156 #define APECS_MEM_B2BCR                 (IDENT_ADDR + 0x180000A40UL)
 157 #define APECS_MEM_B3BCR                 (IDENT_ADDR + 0x180000A60UL)
 158 #define APECS_MEM_B4BCR                 (IDENT_ADDR + 0x180000A80UL)
 159 #define APECS_MEM_B5BCR                 (IDENT_ADDR + 0x180000AA0UL)
 160 #define APECS_MEM_B6BCR                 (IDENT_ADDR + 0x180000AC0UL)
 161 #define APECS_MEM_B7BCR                 (IDENT_ADDR + 0x180000AE0UL)
 162 #define APECS_MEM_B8BCR                 (IDENT_ADDR + 0x180000B00UL)
 163 
 164 /* Bank x Timing Register A */
 165 #define APECS_MEM_B0TRA                 (IDENT_ADDR + 0x180000C00UL)
 166 #define APECS_MEM_B1TRA                 (IDENT_ADDR + 0x180000C20UL)
 167 #define APECS_MEM_B2TRA                 (IDENT_ADDR + 0x180000C40UL)
 168 #define APECS_MEM_B3TRA                 (IDENT_ADDR + 0x180000C60UL)
 169 #define APECS_MEM_B4TRA                 (IDENT_ADDR + 0x180000C80UL)
 170 #define APECS_MEM_B5TRA                 (IDENT_ADDR + 0x180000CA0UL)
 171 #define APECS_MEM_B6TRA                 (IDENT_ADDR + 0x180000CC0UL)
 172 #define APECS_MEM_B7TRA                 (IDENT_ADDR + 0x180000CE0UL)
 173 #define APECS_MEM_B8TRA                 (IDENT_ADDR + 0x180000D00UL)
 174 
 175 /* Bank x Timing Register B */
 176 #define APECS_MEM_B0TRB                 (IDENT_ADDR + 0x180000E00UL)
 177 #define APECS_MEM_B1TRB                 (IDENT_ADDR + 0x180000E20UL)
 178 #define APECS_MEM_B2TRB                 (IDENT_ADDR + 0x180000E40UL)
 179 #define APECS_MEM_B3TRB                 (IDENT_ADDR + 0x180000E60UL)
 180 #define APECS_MEM_B4TRB                 (IDENT_ADDR + 0x180000E80UL)
 181 #define APECS_MEM_B5TRB                 (IDENT_ADDR + 0x180000EA0UL)
 182 #define APECS_MEM_B6TRB                 (IDENT_ADDR + 0x180000EC0UL)
 183 #define APECS_MEM_B7TRB                 (IDENT_ADDR + 0x180000EE0UL)
 184 #define APECS_MEM_B8TRB                 (IDENT_ADDR + 0x180000F00UL)
 185 
 186 
 187 /*
 188  * Memory spaces:
 189  */
 190 #define APECS_IACK_SC                   (IDENT_ADDR + 0x1b0000000UL)
 191 #define APECS_CONF                      (IDENT_ADDR + 0x1e0000000UL)
 192 #define APECS_IO                        (IDENT_ADDR + 0x1c0000000UL)
 193 #define APECS_SPARSE_MEM                (IDENT_ADDR + 0x200000000UL)
 194 #define APECS_DENSE_MEM                 (IDENT_ADDR + 0x300000000UL)
 195 
 196 /*
 197  * Bit definitions for I/O Controller status register 0:
 198  */
 199 #define APECS_IOC_STAT0_CMD             0xf
 200 #define APECS_IOC_STAT0_ERR             (1<<4)
 201 #define APECS_IOC_STAT0_LOST            (1<<5)
 202 #define APECS_IOC_STAT0_THIT            (1<<6)
 203 #define APECS_IOC_STAT0_TREF            (1<<7)
 204 #define APECS_IOC_STAT0_CODE_SHIFT      8
 205 #define APECS_IOC_STAT0_CODE_MASK       0x7
 206 #define APECS_IOC_STAT0_P_NBR_SHIFT     13
 207 #define APECS_IOC_STAT0_P_NBR_MASK      0x7ffff
 208 
 209 #define HAE_ADDRESS     APECS_IOC_HAXR1
 210 
 211 #ifdef __KERNEL__
 212 
 213 /*
 214  * Translate physical memory address as seen on (PCI) bus into
 215  * a kernel virtual address and vv.
 216  */
 217 extern inline unsigned long virt_to_bus(void * address)
     /*  */
 218 {
 219         unsigned long paddr = virt_to_phys(address);
 220 #ifdef CONFIG_ALPHA_XL
 221         if (paddr < APECS_XL_DMA_WIN1_SIZE)
 222           return paddr + APECS_XL_DMA_WIN1_BASE;
 223         else
 224           return paddr + APECS_XL_DMA_WIN2_BASE; /* win 2 xlates to 0 also */
 225 #else /* CONFIG_ALPHA_XL */
 226         return paddr + APECS_DMA_WIN_BASE;
 227 #endif /* CONFIG_ALPHA_XL */
 228 }
 229 
 230 extern inline void * bus_to_virt(unsigned long address)
     /*  */
 231 {
 232         /*
 233          * This check is a sanity check but also ensures that bus
 234          * address 0 maps to virtual address 0 which is useful to
 235          * detect null "pointers" (the NCR driver is much simpler if
 236          * NULL pointers are preserved).
 237          */
 238 #ifdef CONFIG_ALPHA_XL
 239         if (address < APECS_XL_DMA_WIN1_BASE)
 240                 return 0;
 241         else if (address < (APECS_XL_DMA_WIN1_BASE + APECS_XL_DMA_WIN1_SIZE))
 242                 return phys_to_virt(address - APECS_XL_DMA_WIN1_BASE);
 243         else /* should be more checking here, maybe? */
 244                 return phys_to_virt(address - APECS_XL_DMA_WIN2_BASE);
 245 #else /* CONFIG_ALPHA_XL */
 246         if (address < APECS_DMA_WIN_BASE)
 247                 return 0;
 248         return phys_to_virt(address - APECS_DMA_WIN_BASE);
 249 #endif /* CONFIG_ALPHA_XL */
 250 }
 251 
 252 /*
 253  * I/O functions:
 254  *
 255  * Unlike Jensen, the APECS machines have no concept of local
 256  * I/O---everything goes over the PCI bus.
 257  *
 258  * There is plenty room for optimization here.  In particular,
 259  * the Alpha's insb/insw/extb/extw should be useful in moving
 260  * data to/from the right byte-lanes.
 261  */
 262 
 263 #define vuip    volatile unsigned int *
 264 
 265 extern inline unsigned int __inb(unsigned long addr)
     /*  */
 266 {
 267         long result = *(vuip) ((addr << 5) + APECS_IO + 0x00);
 268         result >>= (addr & 3) * 8;
 269         return 0xffUL & result;
 270 }
 271 
 272 extern inline void __outb(unsigned char b, unsigned long addr)
     /*  */
 273 {
 274         unsigned int w;
 275 
 276         asm ("insbl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b));
 277         *(vuip) ((addr << 5) + APECS_IO + 0x00) = w;
 278         mb();
 279 }
 280 
 281 extern inline unsigned int __inw(unsigned long addr)
     /*  */
 282 {
 283         long result = *(vuip) ((addr << 5) + APECS_IO + 0x08);
 284         result >>= (addr & 3) * 8;
 285         return 0xffffUL & result;
 286 }
 287 
 288 extern inline void __outw(unsigned short b, unsigned long addr)
     /*  */
 289 {
 290         unsigned int w;
 291 
 292         asm ("inswl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b));
 293         *(vuip) ((addr << 5) + APECS_IO + 0x08) = w;
 294         mb();
 295 }
 296 
 297 extern inline unsigned int __inl(unsigned long addr)
     /*  */
 298 {
 299         return *(vuip) ((addr << 5) + APECS_IO + 0x18);
 300 }
 301 
 302 extern inline void __outl(unsigned int b, unsigned long addr)
     /*  */
 303 {
 304         *(vuip) ((addr << 5) + APECS_IO + 0x18) = b;
 305         mb();
 306 }
 307 
 308 
 309 /*
 310  * Memory functions.  64-bit and 32-bit accesses are done through
 311  * dense memory space, everything else through sparse space.
 312  */
 313 extern inline unsigned long __readb(unsigned long addr)
     /*  */
 314 {
 315         unsigned long result, shift, msb;
 316 
 317         shift = (addr & 0x3) * 8;
 318         if (addr >= (1UL << 24)) {
 319                 msb = addr & 0xf8000000;
 320                 addr -= msb;
 321                 if (msb != hae.cache) {
 322                         set_hae(msb);
 323                 }
 324         }
 325         result = *(vuip) ((addr << 5) + APECS_SPARSE_MEM + 0x00);
 326         result >>= shift;
 327         return 0xffUL & result;
 328 }
 329 
 330 extern inline unsigned long __readw(unsigned long addr)
     /*  */
 331 {
 332         unsigned long result, shift, msb;
 333 
 334         shift = (addr & 0x3) * 8;
 335         if (addr >= (1UL << 24)) {
 336                 msb = addr & 0xf8000000;
 337                 addr -= msb;
 338                 if (msb != hae.cache) {
 339                         set_hae(msb);
 340                 }
 341         }
 342         result = *(vuip) ((addr << 5) + APECS_SPARSE_MEM + 0x08);
 343         result >>= shift;
 344         return 0xffffUL & result;
 345 }
 346 
 347 extern inline unsigned long __readl(unsigned long addr)
     /*  */
 348 {
 349         return *(vuip) (addr + APECS_DENSE_MEM);
 350 }
 351 
 352 extern inline void __writeb(unsigned char b, unsigned long addr)
     /*  */
 353 {
 354         unsigned long msb;
 355 
 356         if (addr >= (1UL << 24)) {
 357                 msb = addr & 0xf8000000;
 358                 addr -= msb;
 359                 if (msb != hae.cache) {
 360                         set_hae(msb);
 361                 }
 362         }
 363         *(vuip) ((addr << 5) + APECS_SPARSE_MEM + 0x00) = b * 0x01010101;
 364 }
 365 
 366 extern inline void __writew(unsigned short b, unsigned long addr)
     /*  */
 367 {
 368         unsigned long msb;
 369 
 370         if (addr >= (1UL << 24)) {
 371                 msb = addr & 0xf8000000;
 372                 addr -= msb;
 373                 if (msb != hae.cache) {
 374                         set_hae(msb);
 375                 }
 376         }
 377         *(vuip) ((addr << 5) + APECS_SPARSE_MEM + 0x08) = b * 0x00010001;
 378 }
 379 
 380 extern inline void __writel(unsigned int b, unsigned long addr)
     /*  */
 381 {
 382         *(vuip) (addr + APECS_DENSE_MEM) = b;
 383 }
 384 
 385 #define inb(port) \
 386 (__builtin_constant_p((port))?__inb(port):_inb(port))
 387 
 388 #define outb(x, port) \
 389 (__builtin_constant_p((port))?__outb((x),(port)):_outb((x),(port)))
 390 
 391 #define readl(a)        __readl((unsigned long)(a))
 392 #define writel(v,a)     __writel((v),(unsigned long)(a))
 393 
 394 #undef vuip
 395 
 396 extern unsigned long apecs_init (unsigned long mem_start,
 397                                  unsigned long mem_end);
 398 
 399 #endif /* __KERNEL__ */
 400 
 401 /*
 402  * Data structure for handling APECS machine checks:
 403  */
 404 struct el_apecs_sysdata_mcheck {
 405     unsigned long coma_gcr;
 406     unsigned long coma_edsr;
 407     unsigned long coma_ter;
 408     unsigned long coma_elar;
 409     unsigned long coma_ehar;
 410     unsigned long coma_ldlr;
 411     unsigned long coma_ldhr;
 412     unsigned long coma_base0;
 413     unsigned long coma_base1;
 414     unsigned long coma_base2;
 415     unsigned long coma_cnfg0;
 416     unsigned long coma_cnfg1;
 417     unsigned long coma_cnfg2;
 418     unsigned long epic_dcsr;
 419     unsigned long epic_pear;
 420     unsigned long epic_sear;
 421     unsigned long epic_tbr1;
 422     unsigned long epic_tbr2;
 423     unsigned long epic_pbr1;
 424     unsigned long epic_pbr2;
 425     unsigned long epic_pmr1;
 426     unsigned long epic_pmr2;
 427     unsigned long epic_harx1;
 428     unsigned long epic_harx2;
 429     unsigned long epic_pmlt;
 430     unsigned long epic_tag0;
 431     unsigned long epic_tag1;
 432     unsigned long epic_tag2;
 433     unsigned long epic_tag3;
 434     unsigned long epic_tag4;
 435     unsigned long epic_tag5;
 436     unsigned long epic_tag6;
 437     unsigned long epic_tag7;
 438     unsigned long epic_data0;
 439     unsigned long epic_data1;
 440     unsigned long epic_data2;
 441     unsigned long epic_data3;
 442     unsigned long epic_data4;
 443     unsigned long epic_data5;
 444     unsigned long epic_data6;
 445     unsigned long epic_data7;
 446 };
 447 
 448 #define RTC_PORT(x)     (0x70 + (x))
 449 #define RTC_ADDR(x)     (0x80 | (x))
 450 #define RTC_ALWAYS_BCD  0
 451 
 452 #endif /* __ALPHA_APECS__H__ */
/* */
root/include/asm-alpha/apecs.h

INCLUDED FROM

DEFINITIONS
