root/include/asm-sparc/dma.h

/* */

INCLUDED FROM

DEFINITIONS

1. sparc_dma_pause

   1 /* $Id: dma.h,v 1.16 1996/04/25 06:12:54 davem Exp $
   2  * include/asm-sparc/dma.h
   3  *
   4  * Copyright 1995 (C) David S. Miller (davem@caip.rutgers.edu)
   5  */
   6 
   7 #ifndef _ASM_SPARC_DMA_H
   8 #define _ASM_SPARC_DMA_H
   9 
  10 #include <linux/kernel.h>
  11 
  12 #include <asm/vac-ops.h>  /* for invalidate's, etc. */
  13 #include <asm/sbus.h>
  14 #include <asm/delay.h>
  15 #include <asm/oplib.h>
  16 
  17 /* These are irrelevant for Sparc DMA, but we leave it in so that
  18  * things can compile.
  19  */
  20 #define MAX_DMA_CHANNELS 8
  21 #define MAX_DMA_ADDRESS  (~0UL)
  22 #define DMA_MODE_READ    1
  23 #define DMA_MODE_WRITE   2
  24 
  25 /* Useful constants */
  26 #define SIZE_16MB      (16*1024*1024)
  27 #define SIZE_64K       (64*1024)
  28 
  29 /* Structure to describe the current status of DMA registers on the Sparc */
  30 struct sparc_dma_registers {
  31   volatile unsigned long cond_reg;   /* DMA condition register */
  32   volatile char * st_addr;           /* Start address of this transfer */
  33   volatile unsigned long cnt;        /* How many bytes to transfer */
  34   volatile unsigned long dma_test;   /* DMA test register */
  35 };
  36 
  37 /* DVMA chip revisions */
  38 enum dvma_rev {
  39         dvmarev0,
  40         dvmaesc1,
  41         dvmarev1,
  42         dvmarev2,
  43         dvmarev3,
  44         dvmarevplus
  45 };
  46 
  47 #define DMA_HASCOUNT(rev)  ((rev)==dvmaesc1)
  48 
  49 /* Linux DMA information structure, filled during probe. */
  50 struct Linux_SBus_DMA {
  51         struct Linux_SBus_DMA *next;
  52         struct linux_sbus_device *SBus_dev;
  53         struct sparc_dma_registers *regs;
  54 
  55         /* Status, misc info */
  56         int node;                /* Prom node for this DMA device */
  57         int running;             /* Are we doing DMA now? */
  58         int allocated;           /* Are we "owned" by anyone yet? */
  59 
  60         /* Transfer information. */
  61         unsigned long addr;      /* Start address of current transfer */
  62         int nbytes;              /* Size of current transfer */
  63         int realbytes;           /* For splitting up large transfers, etc. */
  64 
  65         /* DMA revision */
  66         enum dvma_rev revision;
  67 };
  68 
  69 extern struct Linux_SBus_DMA *dma_chain;
  70 
  71 /* Broken hardware... */
  72 #define DMA_ISBROKEN(dma)    ((dma)->revision == dvmarev1)
  73 #define DMA_ISESC1(dma)      ((dma)->revision == dvmaesc1)
  74 
  75 /* Main routines in dma.c */
  76 extern void dump_dma_regs(struct sparc_dma_registers *);
  77 extern unsigned long dvma_init(struct linux_sbus *, unsigned long);
  78 
  79 /* Fields in the cond_reg register */
  80 /* First, the version identification bits */
  81 #define DMA_DEVICE_ID    0xf0000000        /* Device identification bits */
  82 #define DMA_VERS0        0x00000000        /* Sunray DMA version */
  83 #define DMA_ESCV1        0x40000000        /* DMA ESC Version 1 */
  84 #define DMA_VERS1        0x80000000        /* DMA rev 1 */
  85 #define DMA_VERS2        0xa0000000        /* DMA rev 2 */
  86 #define DMA_VERSPLUS     0x90000000        /* DMA rev 1 PLUS */
  87 
  88 #define DMA_HNDL_INTR    0x00000001        /* An IRQ needs to be handled */
  89 #define DMA_HNDL_ERROR   0x00000002        /* We need to take an error */
  90 #define DMA_FIFO_ISDRAIN 0x0000000c        /* The DMA FIFO is draining */
  91 #define DMA_INT_ENAB     0x00000010        /* Turn on interrupts */
  92 #define DMA_FIFO_INV     0x00000020        /* Invalidate the FIFO */
  93 #define DMA_ACC_SZ_ERR   0x00000040        /* The access size was bad */
  94 #define DMA_FIFO_STDRAIN 0x00000040        /* DMA_VERS1 Drain the FIFO */
  95 #define DMA_RST_SCSI     0x00000080        /* Reset the SCSI controller */
  96 #define DMA_RST_ENET     DMA_RST_SCSI      /* Reset the ENET controller */
  97 #define DMA_ST_WRITE     0x00000100        /* write from device to memory */
  98 #define DMA_ENABLE       0x00000200        /* Fire up DMA, handle requests */
  99 #define DMA_PEND_READ    0x00000400        /* DMA_VERS1/0/PLUS Pending Read */
 100 #define DMA_DSBL_RD_DRN  0x00001000        /* No EC drain on slave reads */
 101 #define DMA_BCNT_ENAB    0x00002000        /* If on, use the byte counter */
 102 #define DMA_TERM_CNTR    0x00004000        /* Terminal counter */
 103 #define DMA_CSR_DISAB    0x00010000        /* No FIFO drains during csr */
 104 #define DMA_SCSI_DISAB   0x00020000        /* No FIFO drains during reg */
 105 #define DMA_DSBL_WR_INV  0x00020000        /* No EC inval. on slave writes */
 106 #define DMA_ADD_ENABLE   0x00040000        /* Special ESC DVMA optimization */
 107 #define DMA_E_BURST8     0x00040000        /* ENET: SBUS r/w burst size */
 108 #define DMA_BRST_SZ      0x000c0000        /* SCSI: SBUS r/w burst size */
 109 #define DMA_ADDR_DISAB   0x00100000        /* No FIFO drains during addr */
 110 #define DMA_2CLKS        0x00200000        /* Each transfer = 2 clock ticks */
 111 #define DMA_3CLKS        0x00400000        /* Each transfer = 3 clock ticks */
 112 #define DMA_EN_ENETAUI   DMA_3CLKS         /* Put lance into AUI-cable mode */
 113 #define DMA_CNTR_DISAB   0x00800000        /* No IRQ when DMA_TERM_CNTR set */
 114 #define DMA_AUTO_NADDR   0x01000000        /* Use "auto nxt addr" feature */
 115 #define DMA_SCSI_ON      0x02000000        /* Enable SCSI dma */
 116 #define DMA_LOADED_ADDR  0x04000000        /* Address has been loaded */
 117 #define DMA_LOADED_NADDR 0x08000000        /* Next address has been loaded */
 118 
 119 /* Values describing the burst-size property from the PROM */
 120 #define DMA_BURST1       0x01
 121 #define DMA_BURST2       0x02
 122 #define DMA_BURST4       0x04
 123 #define DMA_BURST8       0x08
 124 #define DMA_BURST16      0x10
 125 #define DMA_BURST32      0x20
 126 #define DMA_BURST64      0x40
 127 #define DMA_BURSTBITS    0x7f
 128 
 129 /* Determine highest possible final transfer address given a base */
 130 #define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
 131 
 132 /* Yes, I hack a lot of elisp in my spare time... */
 133 #define DMA_ERROR_P(regs)  ((((regs)->cond_reg) & DMA_HNDL_ERROR))
 134 #define DMA_IRQ_P(regs)    ((((regs)->cond_reg) & DMA_HNDL_INTR))
 135 #define DMA_WRITE_P(regs)  ((((regs)->cond_reg) & DMA_ST_WRITE))
 136 #define DMA_OFF(regs)      ((((regs)->cond_reg) &= (~DMA_ENABLE)))
 137 #define DMA_INTSOFF(regs)  ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
 138 #define DMA_INTSON(regs)   ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
 139 #define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
 140 #define DMA_SETSTART(regs, addr)  ((((regs)->st_addr) = (char *) addr))
 141 #define DMA_BEGINDMA_W(regs) \
 142         ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))
 143 #define DMA_BEGINDMA_R(regs) \
 144         ((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE)))))
 145 
 146 /* For certain DMA chips, we need to disable ints upon irq entry
 147  * and turn them back on when we are done.  So in any ESP interrupt
 148  * handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT
 149  * when leaving the handler.  You have been warned...
 150  */
 151 #define DMA_IRQ_ENTRY(dma, dregs) do { \
 152         if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
 153    } while (0)
 154 
 155 #define DMA_IRQ_EXIT(dma, dregs) do { \
 156         if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \
 157    } while(0)
 158 
 159 /* Pause until counter runs out or BIT isn't set in the DMA condition
 160  * register.
 161  */
 162 extern inline void sparc_dma_pause(struct sparc_dma_registers *regs,
     /*  */
 163                                    unsigned long bit)
 164 {
 165         int ctr = 50000;   /* Let's find some bugs ;) */
 166 
 167         /* Busy wait until the bit is not set any more */
 168         while((regs->cond_reg&bit) && (ctr>0)) {
 169                 ctr--;
 170                 __delay(5);
 171         }
 172 
 173         /* Check for bogus outcome. */
 174         if(!ctr)
 175                 panic("DMA timeout");
 176 }
 177 
 178 /* Reset the friggin' thing... */
 179 #define DMA_RESET(dma) do { \
 180         struct sparc_dma_registers *regs = dma->regs;                      \
 181         /* Let the current FIFO drain itself */                            \
 182         sparc_dma_pause(regs, (DMA_FIFO_ISDRAIN));                         \
 183         /* Reset the logic */                                              \
 184         regs->cond_reg |= (DMA_RST_SCSI);     /* assert */                 \
 185         __delay(400);                         /* let the bits set ;) */    \
 186         regs->cond_reg &= ~(DMA_RST_SCSI);    /* de-assert */              \
 187         sparc_dma_enable_interrupts(regs);    /* Re-enable interrupts */   \
 188         /* Enable FAST transfers if available */                           \
 189         if(dma->revision>dvmarev1) regs->cond_reg |= DMA_3CLKS;            \
 190         dma->running = 0;                                                  \
 191 } while(0)
 192 
 193 #define for_each_dvma(dma) \
 194         for((dma) = dma_chain; (dma); (dma) = (dma)->next)
 195 
 196 extern int get_dma_list(char *);
 197 extern int request_dma(unsigned int, const char *);
 198 extern void free_dma(unsigned int);
 199 
 200 #endif /* !(_ASM_SPARC_DMA_H) */

/* */