include/asm-sparc/viking.h

/* */
This source file includes following definitions.
viking_flush_icache
viking_flush_dcache
viking_unlock_icache
viking_unlock_dcache
viking_set_bpreg
viking_get_bpreg
viking_get_dcache_ptag
   1 /* $Id: viking.h,v 1.13 1996/04/25 06:13:43 davem Exp $
   2  * viking.h:  Defines specific to the GNU/Viking MBUS module.
   3  *            This is SRMMU stuff.
   4  *
   5  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   6  */
   7 #ifndef _SPARC_VIKING_H
   8 #define _SPARC_VIKING_H
   9 
  10 #include <asm/mxcc.h>
  11 
  12 /* Bits in the SRMMU control register for GNU/Viking modules.
  13  *
  14  * -----------------------------------------------------------
  15  * |impl-vers| RSV |TC|AC|SP|BM|PC|MBM|SB|IC|DC|PSO|RSV|NF|ME|
  16  * -----------------------------------------------------------
  17  *  31     24 23-17 16 15 14 13 12 11  10  9  8  7  6-2  1  0
  18  *
  19  * TC: Tablewalk Cacheable -- 0 = Twalks are not cacheable in E-cache
  20  *                            1 = Twalks are cacheable in E-cache
  21  *
  22  * GNU/Viking will only cache tablewalks in the E-cache (mxcc) if present
  23  * and never caches them internally (or so states the docs).  Therefore
  24  * for machines lacking an E-cache (ie. in MBUS mode) this bit must
  25  * remain cleared.
  26  *
  27  * AC: Alternate Cacheable -- 0 = Passthru physical accesses not cacheable
  28  *                            1 = Passthru physical accesses cacheable
  29  *
  30  * This indicates whether accesses are cacheable when no cachable bit
  31  * is present in the pte when the processor is in boot-mode or the
  32  * access does not need pte's for translation (ie. pass-thru ASI's).
  33  * "Cachable" is only referring to E-cache (if present) and not the
  34  * on chip split I/D caches of the GNU/Viking.
  35  *
  36  * SP: SnooP Enable -- 0 = bus snooping off, 1 = bus snooping on
  37  *
  38  * This enables snooping on the GNU/Viking bus.  This must be on
  39  * for the hardware cache consistency mechanisms of the GNU/Viking
  40  * to work at all.  On non-mxcc GNU/Viking modules the split I/D
  41  * caches will snoop regardless of whether they are enabled, this
  42  * takes care of the case where the I or D or both caches are turned
  43  * off yet still contain valid data.  Note also that this bit does
  44  * not affect GNU/Viking store-buffer snoops, those happen if the
  45  * store-buffer is enabled no matter what.
  46  *
  47  * BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode
  48  *
  49  * This indicates whether the GNU/Viking is in boot-mode or not,
  50  * if it is then all instruction fetch physical addresses are
  51  * computed as 0xff0000000 + low 28 bits of requested address.
  52  * GNU/Viking boot-mode does not affect data accesses.  Also,
  53  * in boot mode instruction accesses bypass the split on chip I/D
  54  * caches, they may be cached by the GNU/MXCC if present and enabled.
  55  *
  56  * MBM: MBus Mode -- 0 = not in MBus mode, 1 = in MBus mode
  57  *
  58  * This indicated the GNU/Viking configuration present.  If in
  59  * MBUS mode, the GNU/Viking lacks a GNU/MXCC E-cache.  If it is
  60  * not then the GNU/Viking is on a module VBUS connected directly
  61  * to a GNU/MXCC cache controller.  The GNU/MXCC can be thus connected
  62  * to either an GNU/MBUS (sun4m) or the packet-switched GNU/XBus (sun4d).
  63  *
  64  * SB: StoreBuffer enable -- 0 = store buffer off, 1 = store buffer on
  65  *
  66  * The GNU/Viking store buffer allows the chip to continue execution
  67  * after a store even if the data cannot be placed in one of the
  68  * caches during that cycle.  If disabled, all stores operations
  69  * occur synchronously.
  70  *
  71  * IC: Instruction Cache -- 0 = off, 1 = on
  72  * DC: Data Cache -- 0 = off, 1 = 0n
  73  *
  74  * These bits enable the on-cpu GNU/Viking split I/D caches.  Note,
  75  * as mentioned above, these caches will snoop the bus in GNU/MBUS
  76  * configurations even when disabled to avoid data corruption.
  77  *
  78  * NF: No Fault -- 0 = faults generate traps, 1 = faults don't trap
  79  * ME: MMU enable -- 0 = mmu not translating, 1 = mmu translating
  80  *
  81  */
  82 
  83 #define VIKING_MMUENABLE    0x00000001
  84 #define VIKING_NOFAULT      0x00000002
  85 #define VIKING_PSO          0x00000080
  86 #define VIKING_DCENABLE     0x00000100   /* Enable data cache */
  87 #define VIKING_ICENABLE     0x00000200   /* Enable instruction cache */
  88 #define VIKING_SBENABLE     0x00000400   /* Enable store buffer */
  89 #define VIKING_MMODE        0x00000800   /* MBUS mode */
  90 #define VIKING_PCENABLE     0x00001000   /* Enable parity checking */
  91 #define VIKING_BMODE        0x00002000   
  92 #define VIKING_SPENABLE     0x00004000   /* Enable bus cache snooping */
  93 #define VIKING_ACENABLE     0x00008000   /* Enable alternate caching */
  94 #define VIKING_TCENABLE     0x00010000   /* Enable table-walks to be cached */
  95 
  96 /*
  97  * GNU/Viking Breakpoint Action Register fields.
  98  */
  99 #define VIKING_ACTION_MIX   0x00001000   /* Enable multiple instructions */
 100 
 101 /*
 102  * GNU/Viking Cache Tags.
 103  */
 104 #define VIKING_PTAG_VALID   0x01000000   /* Cache block is valid */
 105 #define VIKING_PTAG_DIRTY   0x00010000   /* Block has been modified */
 106 #define VIKING_PTAG_SHARED  0x00000100   /* Shared with some other cache */
 107 
 108 extern inline void viking_flush_icache(void)
     /*  */
 109 {
 110         __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t" : :
 111                              "i" (ASI_M_IC_FLCLEAR));
 112 }
 113 
 114 extern inline void viking_flush_dcache(void)
     /*  */
 115 {
 116         __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t" : :
 117                              "i" (ASI_M_DC_FLCLEAR));
 118 }
 119 
 120 extern inline void viking_unlock_icache(void)
     /*  */
 121 {
 122         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 123                              "r" (0x80000000), "i" (ASI_M_IC_FLCLEAR));
 124 }
 125 
 126 extern inline void viking_unlock_dcache(void)
     /*  */
 127 {
 128         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 129                              "r" (0x80000000), "i" (ASI_M_DC_FLCLEAR));
 130 }
 131 
 132 extern inline void viking_set_bpreg(unsigned long regval)
     /*  */
 133 {
 134         __asm__ __volatile__("sta %0, [%%g0] %1\n\t" : :
 135                              "r" (regval),
 136                              "i" (ASI_M_ACTION));
 137 }
 138 
 139 extern inline unsigned long viking_get_bpreg(void)
     /*  */
 140 {
 141         unsigned long regval;
 142 
 143         __asm__ __volatile__("lda [%%g0] %1, %0\n\t" :
 144                              "=r" (regval) :
 145                              "i" (ASI_M_ACTION));
 146         return regval;
 147 }
 148 
 149 extern inline void viking_get_dcache_ptag(int set, int block,
     /*  */
 150                                           unsigned long *data)
 151 {
 152         unsigned long ptag = ((set & 0x7f) << 5) | ((block & 0x3) << 26) |
 153                              0x80000000;
 154         unsigned long info, page;
 155 
 156         __asm__ __volatile__ ("ldda [%2] %3, %%g2\n\t"
 157                               "or %%g0, %%g2, %0\n\t"
 158                               "or %%g0, %%g3, %1\n\t" :
 159                               "=r" (info), "=r" (page) :
 160                               "r" (ptag), "i" (ASI_M_DATAC_TAG) :
 161                               "g2", "g3");
 162         data[0] = info;
 163         data[1] = page;
 164 }
 165 
 166 #endif /* !(_SPARC_VIKING_H) */
/* */
root/include/asm-sparc/viking.h

INCLUDED FROM

DEFINITIONS
