taglinefilesource code
sun4m_interrupts38arch/sparc/kernel/sun4m_irq.cstruct sun4m_intregs *sun4m_interrupts;
sun4m_interrupts103arch/sparc/kernel/sun4m_irq.csun4m_interrupts->set = mask;
sun4m_interrupts105arch/sparc/kernel/sun4m_irq.csun4m_interrupts->cpu_intregs[cpu].set = mask;
sun4m_interrupts122arch/sparc/kernel/sun4m_irq.csun4m_interrupts->clear = mask;
sun4m_interrupts124arch/sparc/kernel/sun4m_irq.csun4m_interrupts->cpu_intregs[cpu].clear = mask;
sun4m_interrupts128arch/sparc/kernel/sun4m_irq.csun4m_interrupts->clear = SUN4M_INT_FLOPPY;
sun4m_interrupts138arch/sparc/kernel/sun4m_irq.csun4m_interrupts->cpu_intregs[cpu].set = mask;
sun4m_interrupts146arch/sparc/kernel/sun4m_irq.csun4m_interrupts->cpu_intregs[cpu].clear = mask;
sun4m_interrupts151arch/sparc/kernel/sun4m_irq.csun4m_interrupts->undirected_target = cpu;
sun4m_interrupts259arch/sparc/kernel/sun4m_irq.csun4m_interrupts->set = SUN4M_INT_E14;
sun4m_interrupts295arch/sparc/kernel/sun4m_irq.csun4m_interrupts = sparc_alloc_io(int_regs[0].phys_addr, 0,
sun4m_interrupts304arch/sparc/kernel/sun4m_irq.csun4m_interrupts->set = ~SUN4M_INT_MASKALL;
sun4m_interrupts306arch/sparc/kernel/sun4m_irq.csun4m_interrupts->cpu_intregs[i].clear = ~0x17fff;
sun4m_interrupts320arch/sparc/kernel/sun4m_irq.cirq_rcvreg = &sun4m_interrupts->undirected_target;
sun4m_interrupts321arch/sparc/kernel/sun4m_irq.csun4m_interrupts->undirected_target = 0;
sun4m_interrupts121include/asm-sparc/asmmacro.hset  C_LABEL(sun4m_interrupts), %l5; \
sun4m_interrupts83include/asm-sparc/irq.hextern struct sun4m_intregs *sun4m_interrupts;