include/asm-sparc/irq.h

/* */
   1 /* $Id: irq.h,v 1.13 1996/04/25 06:13:09 davem Exp $
   2  * irq.h: IRQ registers on the Sparc.
   3  *
   4  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   5  */
   6 
   7 #ifndef _SPARC_IRQ_H
   8 #define _SPARC_IRQ_H
   9 
  10 #include <linux/linkage.h>
  11 
  12 #include <asm/system.h>     /* For NCPUS */
  13 
  14 #define NR_IRQS    15
  15 
  16 /* Dave Redman (djhr@tadpole.co.uk)
  17  * changed these to function pointers.. it saves cycles and will allow
  18  * the irq dependencies to be split into different files at a later date
  19  * sun4c_irq.c, sun4m_irq.c etc so we could reduce the kernel size.
  20  */
  21 extern void (*disable_irq)(unsigned int);
  22 extern void (*enable_irq)(unsigned int);
  23 extern void (*clear_clock_irq)( void );
  24 extern void (*clear_profile_irq)( void );
  25 extern void (*load_profile_irq)( unsigned int timeout );
  26 extern void (*init_timers)(void (*lvl10_irq)(int, void *, struct pt_regs *));
  27 extern void claim_ticker14(void (*irq_handler)(int, void *, struct pt_regs *),
  28                            int irq,
  29                            unsigned int timeout);
  30 
  31 #ifdef __SMP__
  32 extern void (*set_cpu_int)(int, int);
  33 extern void (*clear_cpu_int)(int, int);
  34 extern void (*set_irq_udt)(int);
  35 #endif
  36 
  37 extern int request_fast_irq(unsigned int irq, void (*handler)(int, void *, struct pt_regs *), unsigned long flags, const char *devname);
  38 
  39 /* On the sun4m, just like the timers, we have both per-cpu and master
  40  * interrupt registers.
  41  */
  42 
  43 /* These registers are used for sending/receiving irqs from/to
  44  * different cpu's.
  45  */
  46 struct sun4m_intreg_percpu {
  47         unsigned int tbt;        /* Interrupts still pending for this cpu. */
  48 
  49         /* These next two registers are WRITE-ONLY and are only
  50          * "on bit" sensitive, "off bits" written have NO affect.
  51          */
  52         unsigned int clear;  /* Clear this cpus irqs here. */
  53         unsigned int set;    /* Set this cpus irqs here. */
  54         unsigned char space[PAGE_SIZE - 12];
  55 };
  56 
  57 /*
  58  * djhr
  59  * Actually the clear and set fields in this struct are misleading..
  60  * according to the SLAVIO manual (and the same applies for the SEC)
  61  * the clear field clears bits in the mask which will ENABLE that IRQ
  62  * the set field sets bits in the mask to DISABLE the IRQ.
  63  *
  64  * Also the undirected_xx address in the SLAVIO is defined as
  65  * RESERVED and write only..
  66  *
  67  * DAVEM_NOTE: The SLAVIO only specifies behavior on uniprocessor
  68  *             sun4m machines, for MP the layout makes more sense.
  69  */
  70 struct sun4m_intregs {
  71         struct sun4m_intreg_percpu cpu_intregs[NCPUS];
  72         unsigned int tbt;                /* IRQ's that are still pending. */
  73         unsigned int irqs;               /* Master IRQ bits. */
  74 
  75         /* Again, like the above, two these registers are WRITE-ONLY. */
  76         unsigned int clear;              /* Clear master IRQ's by setting bits here. */
  77         unsigned int set;                /* Set master IRQ's by setting bits here. */
  78 
  79         /* This register is both READ and WRITE. */
  80         unsigned int undirected_target;  /* Which cpu gets undirected irqs. */
  81 };
  82 
  83 extern struct sun4m_intregs *sun4m_interrupts;
  84 
  85 /* 
  86  * Bit field defines for the interrupt registers on various
  87  * Sparc machines.
  88  */
  89 
  90 /* The sun4c interrupt register. */
  91 #define SUN4C_INT_ENABLE  0x01     /* Allow interrupts. */
  92 #define SUN4C_INT_E14     0x80     /* Enable level 14 IRQ. */
  93 #define SUN4C_INT_E10     0x20     /* Enable level 10 IRQ. */
  94 #define SUN4C_INT_E8      0x10     /* Enable level 8 IRQ. */
  95 #define SUN4C_INT_E6      0x08     /* Enable level 6 IRQ. */
  96 #define SUN4C_INT_E4      0x04     /* Enable level 4 IRQ. */
  97 #define SUN4C_INT_E1      0x02     /* Enable level 1 IRQ. */
  98 
  99 /* Dave Redman (djhr@tadpole.co.uk)
 100  * The sun4m interrupt registers.
 101  */
 102 #define SUN4M_INT_ENABLE        0x80000000
 103 #define SUN4M_INT_E14           0x00000080
 104 #define SUN4M_INT_E10           0x00080000
 105 
 106 #define SUN4M_HARD_INT(x)       (0x000000001 << (x))
 107 #define SUN4M_SOFT_INT(x)       (0x000010000 << (x))
 108 
 109 #define SUN4M_INT_MASKALL       0x80000000        /* mask all interrupts */
 110 #define SUN4M_INT_MODULE_ERR    0x40000000        /* module error */
 111 #define SUN4M_INT_M2S_WRITE     0x20000000        /* write buffer error */
 112 #define SUN4M_INT_ECC           0x10000000        /* ecc memory error */
 113 #define SUN4M_INT_FLOPPY        0x00400000        /* floppy disk */
 114 #define SUN4M_INT_MODULE        0x00200000        /* module interrupt */
 115 #define SUN4M_INT_VIDEO         0x00100000        /* onboard video */
 116 #define SUN4M_INT_REALTIME      0x00080000        /* system timer */
 117 #define SUN4M_INT_SCSI          0x00040000        /* onboard scsi */
 118 #define SUN4M_INT_AUDIO         0x00020000        /* audio/isdn */
 119 #define SUN4M_INT_ETHERNET      0x00010000        /* onboard ethernet */
 120 #define SUN4M_INT_SERIAL        0x00008000        /* serial ports */
 121 #define SUN4M_INT_KBDMS         0x00004000        /* keyboard/mouse */
 122 #define SUN4M_INT_SBUSBITS      0x00003F80        /* sbus int bits */
 123 
 124 #define SUN4M_INT_SBUS(x)       (1 << (x+7))
 125 
 126 #endif
/* */
root/include/asm-sparc/irq.h

INCLUDED FROM
