root/include/asm-sparc/psr.h

/* */

INCLUDED FROM

   1 /* psr.h: This file holds the macros for masking off various parts of
   2           the processor status register on the Sparc. This is valid
   3           for Version 8. On the V9 this is renamed to the PSTATE
   4           register and its members are accessed as fields like
   5           PSTATE.PRIV for the current CPU privilege level.
   6 
   7    Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu)
   8 */
   9 
  10 #ifndef __LINUX_SPARC_PSR_H
  11 #define __LINUX_SPARC_PSR_H
  12 
  13 #define __LINUX_SPARC_V8  /* duh */
  14 
  15 #ifdef __LINUX_SPARC_V8
  16 
  17 /* The Sparc PSR fields are laid out as the following:
  18 
  19     ------------------------------------------------------------------------
  20     | impl  | vers  | icc   | resv  | EC | EF | PIL  | S | PS | ET |  CWP  |
  21 bits| 31-28 | 27-24 | 23-20 | 19-14 | 13 | 12 | 11-8 | 7 | 6  | 5  |  4-0  |
  22     ------------------------------------------------------------------------
  23 
  24    The PSR can only be directly be written/read by the privileged instructions
  25    'rd' and 'wr'. Certain fields are changed as a side effect due to the 'Ticc',
  26    'save', 'restore', and 'rett' instructions. Also the integer condition codes
  27    'icc' are modified by various arithmetic instructions.
  28 
  29    For example:  wr  %o2, or'd_bit_pattern, %psr
  30                  rd  %psr, %o3
  31 
  32 */
  33 
  34 #define PSR_CWP     0x0000001f         /* current window pointer     */
  35 #define PSR_ET      0x00000020         /* enable traps field         */
  36 #define PSR_PS      0x00000040         /* previous privilege level   */
  37 #define PSR_S       0x00000080         /* current privilege level    */
  38 #define PSR_PIL     0x00000f00         /* processor interrupt level  */
  39 #define PSR_EF      0x00001000         /* enable floating point      */
  40 #define PSR_EC      0x00002000         /* enable co-processor        */
  41 #define PSR_ICC     0x00f00000         /* integer condition codes    */
  42 #define PSR_C       0x00100000         /* carry bit                  */
  43 #define PSR_V       0x00200000         /* overflow bit               */
  44 #define PSR_Z       0x00400000         /* zero bit                   */
  45 #define PSR_N       0x00800000         /* negative bit               */
  46 #define PSR_VERS    0x0f000000         /* cpu-version field          */
  47 #define PSR_IMPL    0xf0000000         /* cpu-implementation field   */
  48 
  49 #endif /* !(__LINUX_SPARC_V8) */
  50 
  51 #ifdef __LINUX_SPARC_V9
  52 
  53 /* The information available in the %psr on the V8 is spread amongst
  54    a whole bunch of registers on the V9. The main one being PSTATE.
  55 
  56      --------------------------------------------------------
  57      |  CLE  | TLE |  MM  | RED | PEF | AM | PRIV | IE | AG |
  58 bits |   9   |  8  |  7-6 |  5  |  4  |  3 |   2  |  1 |  0 |
  59      --------------------------------------------------------
  60 
  61    Writes and reads to PSTATE are done via 'wrpr' and 'rdpr' instructions.
  62 
  63    For example:  wrpr %o2, or'd_bit_pattern, %pstate
  64                  rdpr %pstate, %o3
  65 */
  66 
  67 #define PSTATE_AG    0x001   /* Alternate Globals             */
  68 #define PSTATE_IE    0x002   /* Interrupt Enable              */
  69 #define PSTATE_PRIV  0x004   /* Current privilege level       */
  70 #define PSTATE_AM    0x008   /* Address mask (data reads can  */
  71                              /* be chosen to be either big or */
  72                              /* little endian on V9).         */
  73 #define PSTATE_PEF   0x010   /* enable floating point         */
  74 #define PSTATE_RED   0x020   /* RED trap state (set if trap   */
  75                              /* trap_level == max_tl).        */
  76 #define PSTATE_MM    0x0c0   /* Memory model (Total Store     */
  77                              /* Order=0, Partial Store Order  */
  78                              /* =1 or Relaxed Memory Order=2) */
  79 #define PSTATE_TLE   0x100   /* Trap Little Endian            */
  80 #define PSTATE_CLE   0x200   /* Current Little Endian         */
  81 
  82 
  83 /* The Version Register holds vendor information for the chip:
  84 
  85     ---------------------------------------------------------------------------
  86     | manufacturer | implementation | mask | reserved | maxtl | resv | maxwin |
  87 bits|  63-48       |   47-32        | 31-24|   23-16  | 15-8  | 7-5  |  4-0   |
  88     ---------------------------------------------------------------------------
  89 
  90 */
  91 
  92 #define VERS_MAXWIN  0x000000000000001f     /* 'nwindows' on this chip       */
  93 #define VERS_MAXTL   0x00000000000ff000     /* Maximum Trap-level supported  */
  94 #define VERS_MASK    0x0000000ff0000000     /* impl. dep. chip mask revision */
  95 #define VERS_MANUF   0xffff000000000000     /* Manufacturer ID code          */
  96 
  97 #endif /* !(__LINUX_SPARC_V9) */
  98 
  99 #endif /* !(__LINUX_SPARC_PSR_H) */

/* */