drivers/scsi/aic7xxx.c

/* */
This source file includes following definitions.
debug
debug_config
aic7xxx_setup
aic7xxx_loadseq
aic7xxx_delay
rcs_version
aic7xxx_info
aic7xxx_putscb
aic7xxx_putdmascb
aic7xxx_getscb
aic7xxx_length
aic7xxx_scsirate
aic7xxx_isr
aic7xxx_probe
read_seeprom
detect_maxscb
aic7xxx_register
aic7xxx_detect
aic7xxx_buildscb
aic7xxx_queue
aic7xxx_kill
aic7xxx_abort
aic7xxx_reset
aic7xxx_biosparam
   1 /*+M*************************************************************************
   2  * Adaptec 274x/284x/294x device driver for Linux.
   3  *
   4  * Copyright (c) 1994 John Aycock
   5  *   The University of Calgary Department of Computer Science.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2, or (at your option)
  10  * any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; see the file COPYING.  If not, write to
  19  * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  20  *
  21  * Sources include the Adaptec 1740 driver (aha1740.c), the Ultrastor 24F
  22  * driver (ultrastor.c), various Linux kernel source, the Adaptec EISA
  23  * config file (!adp7771.cfg), the Adaptec AHA-2740A Series User's Guide,
  24  * the Linux Kernel Hacker's Guide, Writing a SCSI Device Driver for Linux,
  25  * the Adaptec 1542 driver (aha1542.c), the Adaptec EISA overlay file
  26  * (adp7770.ovl), the Adaptec AHA-2740 Series Technical Reference Manual,
  27  * the Adaptec AIC-7770 Data Book, the ANSI SCSI specification, the
  28  * ANSI SCSI-2 specification (draft 10c), ...
  29  *
  30  * ----------------------------------------------------------------
  31  *  Modified to include support for wide and twin bus adapters,
  32  *  DMAing of SCBs, tagged queueing, IRQ sharing, bug fixes,
  33  *  and other rework of the code.
  34  *
  35  *  Parts of this driver are based on the FreeBSD driver by Justin
  36  *  T. Gibbs.
  37  *
  38  *  A Boot time option was also added for not resetting the scsi bus.
  39  *
  40  *    Form:  aic7xxx=extended,no_reset
  41  *
  42  *    -- Daniel M. Eischen, deischen@iworks.InterWorks.org, 04/03/95
  43  *
  44  *  $Id: aic7xxx.c,v 1.49 1995/06/28 05:41:09 deang Exp $
  45  *-M*************************************************************************/
  46 
  47 #ifdef MODULE
  48 #include <linux/module.h>
  49 #endif
  50 
  51 #include <stdarg.h>
  52 #include <asm/io.h>
  53 #include <linux/string.h>
  54 #include <linux/kernel.h>
  55 #include <linux/ioport.h>
  56 #include <linux/bios32.h>
  57 #include <linux/delay.h>
  58 #include <linux/sched.h>
  59 #include <linux/pci.h>
  60 #include <linux/proc_fs.h>
  61 #include "../block/blk.h"
  62 #include "sd.h"
  63 #include "scsi.h"
  64 #include "hosts.h"
  65 #include "aic7xxx.h"
  66 
  67 #define AIC7XXX_C_VERSION  "$Revision: 1.49 $"
  68 
  69 #define NUMBER(arr)     (sizeof(arr) / sizeof(arr[0]))
  70 #define MIN(a,b) ((a < b) ? a : b)
  71 
  72 /*
  73  * Defines for PCI bus support, testing twin bus support, DMAing of
  74  * SCBs, and tagged queueing.
  75  *
  76  *   o PCI bus support - this has been implemented and working since
  77  *     the December 1, 1994 release of this driver. If you don't have
  78  *     a PCI bus and do not wish to configure your kernel with PCI
  79  *     support, then make sure this define is set to the cprrect
  80  *     define for PCI support (CONFIG_PCI) and configure your kernel
  81  *     without PCI support (make config).
  82  *
  83  *   o Twin bus support - this has been tested and does work.
  84  *
  85  *   o DMAing of SCBs - thanks to Kai Makisara, this now works
  86  *
  87  *   o Tagged queueing - this driver is capable of tagged queueing
  88  *     but I am unsure as to how well the higher level driver implements
  89  *     tagged queueing. Therefore, the maximum commands per lun is
  90  *     set to 2. If you want to implement tagged queueing, ensure
  91  *     this define is not commented out.
  92  *
  93  *   o Sharing IRQs - allowed for sharing of IRQs. This will allow
  94  *     for multiple aic7xxx host adapters sharing the same IRQ, but
  95  *     not for sharing IRQs with other devices. The higher level
  96  *     PCI code and interrupt handling needs to be modified to
  97  *     support this.
  98  *
  99  *  Daniel M. Eischen, deischen@iworks.InterWorks.org, 03/11/95
 100  */
 101 
 102 /* Uncomment this for testing twin bus support. */
 103 #define AIC7XXX_TWIN_SUPPORT
 104 
 105 /* Uncomment this for DMAing of SCBs. */
 106 #define AIC7XXX_USE_DMA
 107 
 108 /* Uncomment this for tagged queueing. */
 109 /* #define AIC7XXX_TAGGED_QUEUEING */
 110 
 111 /* Uncomment this for allowing sharing of IRQs. */
 112 #define AIC7XXX_SHARE_IRQS
 113 
 114 /* Set this to the delay in seconds after SCSI bus reset. */
 115 #define AIC7XXX_RESET_DELAY 15
 116 
 117 /*
 118  * Uncomment this to always use scatter/gather lists.
 119  * *NOTE: The sequencer must be changed also!
 120  */
 121 #define AIC7XXX_USE_SG
 122 
 123 /*
 124  * Controller type and options
 125  */
 126 typedef enum {
 127   AIC_NONE,
 128   AIC_274x,    /* EISA aic7770 */
 129   AIC_284x,    /* VLB  aic7770 */
 130   AIC_7870,    /* PCI  aic7870 */
 131   AIC_7850,    /* PCI  aic7850 */
 132   AIC_7872     /* PCI  aic7870 on 394x */
 133 } aha_type;
 134 
 135 typedef enum {
 136   AIC_SINGLE,  /* Single Channel */
 137   AIC_TWIN,    /* Twin Channel */
 138   AIC_WIDE     /* Wide Channel */
 139 } aha_bus_type;
 140 
 141 typedef enum {
 142   AIC_UNKNOWN,
 143   AIC_ENABLED,
 144   AIC_DISABLED
 145 } aha_status_type;
 146 
 147 /*
 148  * There should be a specific return value for this in scsi.h, but
 149  * it seems that most drivers ignore it.
 150  */
 151 #define DID_UNDERFLOW   DID_ERROR
 152 
 153 /*
 154  *  What we want to do is have the higher level scsi driver requeue
 155  *  the command to us. There is no specific driver status for this
 156  *  condition, but the higher level scsi driver will requeue the
 157  *  command on a DID_BUS_BUSY error.
 158  */
 159 #define DID_RETRY_COMMAND DID_BUS_BUSY
 160 
 161 /*
 162  * EISA/VL-bus stuff
 163  */
 164 #define MINSLOT         1
 165 #define MAXSLOT         15
 166 #define SLOTBASE(x)     ((x) << 12)
 167 #define MAXIRQ          15
 168 
 169 /*
 170  * Standard EISA Host ID regs  (Offset from slot base)
 171  */
 172 #define HID0(x)         ((x) + 0xC80)   /* 0,1: msb of ID2, 2-7: ID1      */
 173 #define HID1(x)         ((x) + 0xC81)   /* 0-4: ID3, 5-7: LSB ID2         */
 174 #define HID2(x)         ((x) + 0xC82)   /* product                        */
 175 #define HID3(x)         ((x) + 0xC83)   /* firmware revision              */
 176 
 177 /*
 178  * AIC-7770 I/O range to reserve for a card
 179  */
 180 #define MINREG(x)       ((x) + 0xC00ul)
 181 #define MAXREG(x)       ((x) + 0xCBFul)
 182 
 183 /* -------------------- AIC-7770 offset definitions ----------------------- */
 184 
 185 /*
 186  * SCSI Sequence Control (p. 3-11).
 187  * Each bit, when set starts a specific SCSI sequence on the bus
 188  */
 189 #define SCSISEQ(x)              ((x) + 0xC00ul)
 190 #define         TEMODEO         0x80
 191 #define         ENSELO          0x40
 192 #define         ENSELI          0x20
 193 #define         ENRSELI         0x10
 194 #define         ENAUTOATNO      0x08
 195 #define         ENAUTOATNI      0x04
 196 #define         ENAUTOATNP      0x02
 197 #define         SCSIRSTO        0x01
 198 
 199 /*
 200  * SCSI Transfer Control 1 Register (pp. 3-14,15).
 201  * Controls the SCSI module data path.
 202  */
 203 #define SXFRCTL1(x)             ((x) + 0xC02ul)
 204 #define         BITBUCKET       0x80
 205 #define         SWRAPEN         0x40
 206 #define         ENSPCHK         0x20
 207 #define         STIMESEL        0x18
 208 #define         ENSTIMER        0x04
 209 #define         ACTNEGEN        0x02
 210 #define         STPWEN          0x01            /* Powered Termination */
 211 
 212 /*
 213  * SCSI Control Signal Read Register (p. 3-15).
 214  * Reads the actual state of the SCSI bus pins
 215  */
 216 #define SCSISIGI(x)             ((x) + 0xC03ul)
 217 #define         CDI             0x80
 218 #define         IOI             0x40
 219 #define         MSGI            0x20
 220 #define         ATNI            0x10
 221 #define         SELI            0x08
 222 #define         BSYI            0x04
 223 #define         REQI            0x02
 224 #define         ACKI            0x01
 225 
 226 /*
 227  * SCSI Contol Signal Write Register (p. 3-16).
 228  * Writing to this register modifies the control signals on the bus. Only
 229  * those signals that are allowed in the current mode (Initiator/Target) are
 230  * asserted.
 231  */
 232 #define SCSISIGO(x)             ((x) + 0xC03ul)
 233 #define         CDO             0x80
 234 #define         IOO             0x40
 235 #define         MSGO            0x20
 236 #define         ATNO            0x10
 237 #define         SELO            0x08
 238 #define         BSYO            0x04
 239 #define         REQO            0x02
 240 #define         ACKO            0x01
 241 
 242 /*
 243  * SCSI Rate
 244  */
 245 #define SCSIRATE(x)             ((x) + 0xC04ul)
 246 
 247 /*
 248  * SCSI ID (p. 3-18).
 249  * Contains the ID of the board and the current target on the
 250  * selected channel
 251  */
 252 #define SCSIID(x)               ((x) + 0xC05ul)
 253 #define         TID             0xF0            /* Target ID mask */
 254 #define         OID             0x0F            /* Our ID mask */
 255 
 256 /*
 257  * SCSI Status 0 (p. 3-21)
 258  * Contains one set of SCSI Interrupt codes
 259  * These are most likely of interest to the sequencer
 260  */
 261 #define SSTAT0(x)               ((x) + 0xC0Bul)
 262 #define         TARGET          0x80            /* Board is a target */
 263 #define         SELDO           0x40            /* Selection Done */
 264 #define         SELDI           0x20            /* Board has been selected */
 265 #define         SELINGO         0x10            /* Selection In Progress */
 266 #define         SWRAP           0x08            /* 24bit counter wrap */
 267 #define         SDONE           0x04            /* STCNT = 0x000000 */
 268 #define         SPIORDY         0x02            /* SCSI PIO Ready */
 269 #define         DMADONE         0x01            /* DMA transfer completed */
 270 
 271 /*
 272  * Clear SCSI Interrupt 1 (p. 3-23)
 273  * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1.
 274  */
 275 #define CLRSINT1(x)             ((x) + 0xC0Cul)
 276 #define         CLRSELTIMEO     0x80
 277 #define         CLRATNO         0x40
 278 #define         CLRSCSIRSTI     0x20
 279 /*  UNUSED                      0x10 */
 280 #define         CLRBUSFREE      0x08
 281 #define         CLRSCSIPERR     0x04
 282 #define         CLRPHASECHG     0x02
 283 #define         CLRREQINIT      0x01
 284 
 285 /*
 286  * SCSI Status 1 (p. 3-24)
 287  * These interrupt bits are of interest to the kernel driver
 288  */
 289 #define SSTAT1(x)               ((x) + 0xC0Cul)
 290 #define         SELTO           0x80
 291 #define         ATNTARG         0x40
 292 #define         SCSIRSTI        0x20
 293 #define         PHASEMIS        0x10
 294 #define         BUSFREE         0x08
 295 #define         SCSIPERR        0x04
 296 #define         PHASECHG        0x02
 297 #define         REQINIT         0x01
 298 
 299 /*
 300  * SCSI Interrrupt Mode 1 (pp. 3-28,29).
 301  * Set bits in this register enable the corresponding
 302  * interrupt source.
 303  */
 304 #define SIMODE1(x)              ((x) + 0xC11ul)
 305 #define         ENSELTIMO       0x80
 306 #define         ENATNTARG       0x40
 307 #define         ENSCSIRST       0x20
 308 #define         ENPHASEMIS      0x10
 309 #define         ENBUSFREE       0x08
 310 #define         ENSCSIPERR      0x04
 311 #define         ENPHASECHG      0x02
 312 #define         ENREQINIT       0x01
 313 
 314 /*
 315  * Selection/Reselection ID (p. 3-31)
 316  * Upper four bits are the device id. The ONEBIT is set when the re/selecting
 317  * device did not set its own ID.
 318  */
 319 #define SELID(x)                ((x) + 0xC19ul)
 320 #define         SELID_MASK      0xF0
 321 #define         ONEBIT          0x08
 322 /*  UNUSED                      0x07 */
 323 
 324 /*
 325  * Serial EEPROM Control (p. 4-92 in 7870 Databook)
 326  * Controls the reading and writing of an external serial 1-bit
 327  * EEPROM Device.  In order to access the serial EEPROM, you must
 328  * first set the SEEMS bit that generates a request to the memory
 329  * port for access to the serial EEPROM device.  When the memory
 330  * port is not busy servicing another request, it reconfigures
 331  * to allow access to the serial EEPROM.  When this happens, SEERDY
 332  * gets set high to verify that the memory port access has been
 333  * granted.  See aic7xxx_read_eprom for detailed information on
 334  * the protocol necessary to read the serial EEPROM.
 335  */
 336 #define SEECTL(x)               ((x) + 0xC1Eul)
 337 #define         EXTARBACK       0x80
 338 #define         EXTARBREQ       0x40
 339 #define         SEEMS           0x20
 340 #define         SEERDY          0x10
 341 #define         SEECS           0x08
 342 #define         SEECK           0x04
 343 #define         SEEDO           0x02
 344 #define         SEEDI           0x01
 345 
 346 /*
 347  * SCSI Block Control (p. 3-32)
 348  * Controls Bus type and channel selection. In a twin channel configuration
 349  * addresses 0x00-0x1E are gated to the appropriate channel based on this
 350  * register. SELWIDE allows for the coexistence of 8bit and 16bit devices
 351  * on a wide bus.
 352  */
 353 #define SBLKCTL(x)              ((x) + 0xC1Ful)
 354 /*  UNUSED                      0xC0 */
 355 #define         AUTOFLUSHDIS    0x20            /* used for Rev C check */
 356 /*  UNUSED                      0x10 */
 357 #define         SELBUSB         0x08
 358 /*  UNUSED                      0x04 */
 359 #define         SELWIDE         0x02
 360 /*  UNUSED                      0x01 */
 361 #define         SELSINGLE       0x00
 362 
 363 /*
 364  * Sequencer Control (p. 3-33)
 365  * Error detection mode and speed configuration
 366  */
 367 #define SEQCTL(x)               ((x) + 0xC60ul)
 368 #define         PERRORDIS       0x80
 369 #define         PAUSEDIS        0x40
 370 #define         FAILDIS         0x20
 371 #define         FASTMODE        0x10
 372 #define         BRKADRINTEN     0x08
 373 #define         STEP            0x04
 374 #define         SEQRESET        0x02
 375 #define         LOADRAM         0x01
 376 
 377 /*
 378  * Sequencer RAM Data (p. 3-34)
 379  * Single byte window into the Scratch Ram area starting at the address
 380  * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write
 381  * four bytes in sucessesion. The SEQADDRs will increment after the most
 382  * significant byte is written
 383  */
 384 #define SEQRAM(x)               ((x) + 0xC61ul)
 385 
 386 /*
 387  * Sequencer Address Registers (p. 3-35)
 388  * Only the first bit of SEQADDR1 holds addressing information
 389  */
 390 #define SEQADDR0(x)             ((x) + 0xC62ul)
 391 #define SEQADDR1(x)             ((x) + 0xC63ul)
 392 
 393 #define ACCUM(x)                ((x) + 0xC64ul)         /* accumulator */
 394 
 395 /*
 396  * Board Control (p. 3-43)
 397  */
 398 #define BCTL(x)         ((x) + 0xC84ul)
 399 /*   RSVD                       0xF0 */
 400 #define         ACE             0x08    /* Support for external processors */
 401 /*   RSVD                       0x06 */
 402 #define         ENABLE          0x01
 403 
 404 #define BUSSPD(x)               ((x) + 0xC86ul) /* FIFO threshold bits ? */
 405 
 406 /*
 407  * Host Control (p. 3-47) R/W
 408  * Overal host control of the device.
 409  */
 410 #define HCNTRL(x)               ((x) + 0xC87ul)
 411 /*    UNUSED                    0x80 */
 412 #define         POWRDN          0x40
 413 /*    UNUSED                    0x20 */
 414 #define         SWINT           0x10
 415 #define         IRQMS           0x08
 416 #define         PAUSE           0x04
 417 #define         INTEN           0x02
 418 #define         CHIPRST         0x01
 419 #define         REQ_PAUSE       IRQMS | PAUSE | INTEN
 420 #define         UNPAUSE_274X    IRQMS | INTEN
 421 #define         UNPAUSE_284X    INTEN
 422 #define         UNPAUSE_294X    IRQMS | INTEN
 423 
 424 /*
 425  * SCB Pointer (p. 3-49)
 426  * Gate one of the four SCBs into the SCBARRAY window.
 427  */
 428 #define SCBPTR(x)               ((x) + 0xC90ul)
 429 
 430 /*
 431  * Interrupt Status (p. 3-50)
 432  * Status for system interrupts
 433  */
 434 #define INTSTAT(x)              ((x) + 0xC91ul)
 435 #define         SEQINT_MASK     0xF0            /* SEQINT Status Codes */
 436 #define                 BAD_PHASE       0x00
 437 #define                 SEND_REJECT     0x10
 438 #define                 NO_IDENT        0x20
 439 #define                 NO_MATCH        0x30
 440 #define                 MSG_SDTR        0x40
 441 #define                 MSG_WDTR        0x50
 442 #define                 MSG_REJECT      0x60
 443 #define                 BAD_STATUS      0x70
 444 #define                 RESIDUAL        0x80
 445 #define                 ABORT_TAG       0x90
 446 #define                 AWAITING_MSG    0xa0
 447 #define         BRKADRINT 0x08
 448 #define         SCSIINT   0x04
 449 #define         CMDCMPLT  0x02
 450 #define         SEQINT    0x01
 451 #define         INT_PEND  (BRKADRINT | SEQINT | SCSIINT | CMDCMPLT)
 452 
 453 /*
 454  * Hard Error (p. 3-53)
 455  * Reporting of catastrophic errors. You usually cannot recover from
 456  * these without a full board reset.
 457  */
 458 #define ERROR(x)                ((x) + 0xC92ul)
 459 /*    UNUSED                    0xF0 */
 460 #define         PARERR          0x08
 461 #define         ILLOPCODE       0x04
 462 #define         ILLSADDR        0x02
 463 #define         ILLHADDR        0x01
 464 
 465 /*
 466  * Clear Interrupt Status (p. 3-52)
 467  */
 468 #define CLRINT(x)               ((x) + 0xC92ul)
 469 #define         CLRBRKADRINT    0x08
 470 #define         CLRSCSIINT      0x04
 471 #define         CLRCMDINT       0x02
 472 #define         CLRSEQINT       0x01
 473 
 474 /*
 475  * SCB Auto Increment (p. 3-59)
 476  * Byte offset into the SCB Array and an optional bit to allow auto
 477  * incrementing of the address during download and upload operations
 478  */
 479 #define SCBCNT(x)               ((x) + 0xC9Aul)
 480 #define         SCBAUTO         0x80
 481 #define         SCBCNT_MASK     0x1F
 482 
 483 /*
 484  * Queue In FIFO (p. 3-60)
 485  * Input queue for queued SCBs (commands that the seqencer has yet to start)
 486  */
 487 #define QINFIFO(x)              ((x) + 0xC9Bul)
 488 
 489 /*
 490  * Queue In Count (p. 3-60)
 491  * Number of queued SCBs
 492  */
 493 #define QINCNT(x)               ((x) + 0xC9Cul)
 494 
 495 /*
 496  * Queue Out FIFO (p. 3-61)
 497  * Queue of SCBs that have completed and await the host
 498  */
 499 #define QOUTFIFO(x)             ((x) + 0xC9Dul)
 500 
 501 /*
 502  * Queue Out Count (p. 3-61)
 503  * Number of queued SCBs in the Out FIFO
 504  */
 505 #define QOUTCNT(x)              ((x) + 0xC9Eul)
 506 
 507 #define SCBARRAY(x)             ((x) + 0xCA0ul)
 508 
 509 /* ---------------- END AIC-7770 Register Definitions ----------------- */
 510 
 511 /* --------------------- AIC-7870-only definitions -------------------- */
 512 
 513 #define DSPCISTATUS(x)          ((x) + 0xC86ul)
 514 #define         DFTHRESH        0xC0
 515 
 516 /* Scratch RAM offset definitions */
 517 
 518 /* ---------------------- Scratch RAM Offsets ------------------------- */
 519 /* These offsets are either to values that are initialized by the board's
 520  * BIOS or are specified by the Linux sequencer code. If I can figure out
 521  * how to read the EISA configuration info at probe time, the cards could
 522  * be run without BIOS support installed
 523  */
 524 
 525 /*
 526  * 1 byte per target starting at this address for configuration values
 527  */
 528 #define HA_TARG_SCRATCH(x)      ((x) + 0xC20ul)
 529 
 530 /*
 531  * The sequencer will stick the first byte of any rejected message here so
 532  * we can see what is getting thrown away.
 533  */
 534 #define HA_REJBYTE(x)           ((x) + 0xC31ul)
 535 
 536 /*
 537  * Bit vector of targets that have disconnection disabled.
 538  */
 539 #define HA_DISC_DSB             ((x) + 0xc32ul)
 540 
 541 /*
 542  * Length of pending message
 543  */
 544 #define HA_MSG_LEN(x)           ((x) + 0xC34ul)
 545 
 546 /*
 547  * Outgoing Message Body
 548  */
 549 #define HA_MSG_START(x)         ((x) + 0xC35ul)
 550 
 551 /*
 552  * These are offsets into the card's scratch ram. Some of the values are
 553  * specified in the AHA2742 technical reference manual and are initialized
 554  * by the BIOS at boot time.
 555  */
 556 #define HA_ARG_1(x)             ((x) + 0xC4Aul) /* sdtr <-> rate parameters */
 557 #define HA_RETURN_1(x)          ((x) + 0xC4Aul)
 558 #define         SEND_SENSE      0x80
 559 #define         SEND_SDTR       0x80
 560 #define         SEND_WDTR       0x80
 561 #define         SEND_REJ        0x40
 562 
 563 #define HA_SIGSTATE(x)          ((x) + 0xC4Bul) /* value in SCSISIGO */
 564 #define HA_SCBCOUNT(x)          ((x) + 0xC52ul) /* number of hardware SCBs */
 565 
 566 #define HA_FLAGS(x)             ((x) + 0xC53ul) /* TWIN and WIDE bus flags */
 567 #define         SINGLE_BUS      0x00
 568 #define         TWIN_BUS        0x01
 569 #define         WIDE_BUS        0x02
 570 #define         ACTIVE_MSG      0x20
 571 #define         IDENTIFY_SEEN   0x40
 572 #define         RESELECTING     0x80
 573 
 574 #define HA_ACTIVE0(x)           ((x) + 0xC54ul) /* Active bits; targets 0-7 */
 575 #define HA_ACTIVE1(x)           ((x) + 0xC55ul) /* Active bits; targets 8-15 */
 576 #define SAVED_TCL(x)            ((x) + 0xC56ul) /* Saved target, channel, LUN */
 577 #define WAITING_SCBH(x)         ((x) + 0xC57ul) /* Head of disconnected targets list. */
 578 #define WAITING_SCBT(x)         ((x) + 0xC58ul) /* Tail of disconnected targets list. */
 579 
 580 #define HA_SCSICONF(x)          ((x) + 0xC5Aul) /* SCSI config register */
 581 #define HA_INTDEF(x)            ((x) + 0xC5Cul) /* interrupt def'n register */
 582 #define HA_HOSTCONF(x)          ((x) + 0xC5Dul) /* host config def'n register */
 583 
 584 #define MSG_ABORT               0x06
 585 #define MSG_BUS_DEVICE_RESET    0x0c
 586 #define BUS_8_BIT               0x00
 587 #define BUS_16_BIT              0x01
 588 #define BUS_32_BIT              0x02
 589 
 590 
 591 /*
 592  *
 593  * Define the format of the SEEPROM registers (16 bits).
 594  *
 595  */
 596 struct seeprom_config {
 597 
 598 /*
 599  * SCSI ID Configuration Flags
 600  */
 601 #define CFXFER          0x0007          /* synchronous transfer rate */
 602 #define CFSYNCH         0x0008          /* enable synchronous transfer */
 603 #define CFDISC          0x0010          /* enable disconnection */
 604 #define CFWIDEB         0x0020          /* wide bus device */
 605 /* UNUSED               0x00C0 */
 606 #define CFSTART         0x0100          /* send start unit SCSI command */
 607 #define CFINCBIOS       0x0200          /* include in BIOS scan */
 608 #define CFRNFOUND       0x0400          /* report even if not found */
 609 /* UNUSED               0xF800 */
 610   unsigned short device_flags[16];      /* words 0-15 */
 611 
 612 /*
 613  * BIOS Control Bits
 614  */
 615 #define CFSUPREM        0x0001          /* support all removeable drives */
 616 #define CFSUPREMB       0x0002          /* support removeable drives for boot only */
 617 #define CFBIOSEN        0x0004          /* BIOS enabled */
 618 /* UNUSED               0x0008 */
 619 #define CFSM2DRV        0x0010          /* support more than two drives */
 620 /* UNUSED               0x0060 */
 621 #define CFEXTEND        0x0080          /* extended translation enabled */
 622 /* UNUSED               0xFF00 */
 623   unsigned short bios_control;          /* word 16 */
 624 
 625 /*
 626  * Host Adapter Control Bits
 627  */
 628 /* UNUSED               0x0003 */
 629 #define CFWSTERM        0x0008          /* SCSI high byte termination (wide card) */
 630 #define CFSTERM         0x0004          /* SCSI low byte termination (non-wide cards) */
 631 #define CFSPARITY       0x0010          /* SCSI parity */
 632 /* UNUSED               0x0020 */
 633 #define CFRESETB        0x0040          /* reset SCSI bus at IC initialization */
 634 /* UNUSED               0xFF80 */
 635   unsigned short adapter_control;       /* word 17 */
 636 
 637 /*
 638  * Bus Release, Host Adapter ID
 639  */
 640 #define CFSCSIID        0x000F          /* host adapter SCSI ID */
 641 /* UNUSED               0x00F0 */
 642 #define CFBRTIME        0xFF00          /* bus release time */
 643   unsigned short brtime_id;             /* word 18 */
 644 
 645 /*
 646  * Maximum targets
 647  */
 648 #define CFMAXTARG       0x00FF  /* maximum targets */
 649 /* UNUSED               0xFF00 */
 650   unsigned short max_targets;           /* word 19 */
 651 
 652   unsigned short res_1[11];             /* words 20-30 */
 653   unsigned short checksum;              /* word 31 */
 654 
 655 };
 656 
 657 
 658 #define AIC7XXX_DEBUG
 659 
 660 /*
 661  * Pause the sequencer and wait for it to actually stop - this
 662  * is important since the sequencer can disable pausing for critical
 663  * sections.
 664  */
 665 #define PAUSE_SEQUENCER(p) \
 666   outb(p->pause, HCNTRL(p->base));                      \
 667   while ((inb(HCNTRL(p->base)) & PAUSE) == 0)           \
 668     ;                                                   \
 669 
 670 /*
 671  * Unpause the sequencer. Unremarkable, yet done often enough to
 672  * warrant an easy way to do it.
 673  */
 674 #define UNPAUSE_SEQUENCER(p) \
 675   outb(p->unpause, HCNTRL(p->base))
 676 
 677 /*
 678  * Restart the sequencer program from address zero
 679  */
 680 #define RESTART_SEQUENCER(p) \
 681   do {                                                  \
 682     outb(SEQRESET | FASTMODE, SEQCTL(p->base)); \
 683   } while (inb(SEQADDR0(p->base)) != 0 &&               \
 684            inb(SEQADDR1(p->base)) != 0);                \
 685   UNPAUSE_SEQUENCER(p);
 686 
 687 /*
 688  * If an error occurs during a data transfer phase, run the comand
 689  * to completion - it's easier that way - making a note of the error
 690  * condition in this location. This then will modify a DID_OK status
 691  * into an appropriate error for the higher-level SCSI code.
 692  */
 693 #define aic7xxx_error(cmd)      ((cmd)->SCp.Status)
 694 
 695 /*
 696  * Keep track of the targets returned status.
 697  */
 698 #define aic7xxx_status(cmd)     ((cmd)->SCp.sent_command)
 699 
 700 /*
 701  * The position of the SCSI commands scb within the scb array.
 702  */
 703 #define aic7xxx_position(cmd)   ((cmd)->SCp.have_data_in)
 704 
 705 /*
 706  * Since the sequencer code DMAs the scatter-gather structures
 707  * directly from memory, we use this macro to assert that the
 708  * kernel structure hasn't changed.
 709  */
 710 #define SG_STRUCT_CHECK(sg) \
 711   ((char *)&(sg).address - (char *)&(sg) != 0 ||  \
 712    (char *)&(sg).length  - (char *)&(sg) != 8 ||  \
 713    sizeof((sg).address) != 4 ||                   \
 714    sizeof((sg).length)  != 4 ||                   \
 715    sizeof(sg)           != 12)
 716 
 717 /*
 718  * "Static" structures. Note that these are NOT initialized
 719  * to zero inside the kernel - we have to initialize them all
 720  * explicitly.
 721  *
 722  * We support a maximum of one adapter card per IRQ level (see the
 723  * rationale for this above). On an interrupt, use the IRQ as an
 724  * index into aic7xxx_boards[] to locate the card information.
 725  */
 726 static struct Scsi_Host *aic7xxx_boards[MAXIRQ + 1];
 727 
 728 /*
 729  * The driver keeps up to four scb structures per card in memory. Only the
 730  * first 26 bytes of the structure are valid for the hardware, the rest used
 731  * for driver level bookeeping. The driver is further optimized
 732  * so that we only have to download the first 19 bytes since as long
 733  * as we always use S/G, the last fields should be zero anyway.
 734  */
 735 #ifdef AIC7XXX_USE_SG
 736 #define SCB_DOWNLOAD_SIZE       19      /* amount to actually download */
 737 #else
 738 #define SCB_DOWNLOAD_SIZE       26
 739 #endif
 740 
 741 #define SCB_UPLOAD_SIZE         19      /* amount to actually upload */
 742 
 743 struct aic7xxx_scb {
 744 /* ------------    Begin hardware supported fields    ---------------- */
 745 /*1 */  unsigned char control;
 746 #define SCB_NEEDWDTR 0x80                       /* Initiate Wide Negotiation */
 747 #define SCB_NEEDSDTR 0x40                       /* Initiate Sync Negotiation */
 748 #define SCB_NEEDDMA  0x08                       /* SCB needs to be DMA'd from
 749                                                  * from host memory
 750                                                  */
 751 #define SCB_REJ_MDP      0x80                   /* Reject MDP message */
 752 #define SCB_DISEN        0x40                   /* SCB Disconnect enable */
 753 #define SCB_TE           0x20                   /* Tag enable */
 754 /*      RESERVED         0x10 */
 755 #define SCB_WAITING      0x08                   /* Waiting */
 756 #define SCB_DIS          0x04                   /* Disconnected */
 757 #define SCB_TAG_TYPE     0x03
 758 #define         SIMPLE_QUEUE 0x00               /* Simple Queue */
 759 #define         HEAD_QUEUE   0x01               /* Head of Queue */
 760 #define         ORD_QUEUE    0x02               /* Ordered Queue */
 761 /*              ILLEGAL      0x03 */
 762 /*2 */  unsigned char target_channel_lun;       /* 4/1/3 bits */
 763 /*3 */  unsigned char SG_segment_count;
 764 /*7 */  unsigned char SG_list_pointer[4] __attribute__ ((packed));
 765 /*11*/  unsigned char SCSI_cmd_pointer[4] __attribute__ ((packed));
 766 /*12*/  unsigned char SCSI_cmd_length;
 767 /*14*/  unsigned char RESERVED[2];              /* must be zero */
 768 /*15*/  unsigned char target_status;
 769 /*18*/  unsigned char residual_data_count[3];
 770 /*19*/  unsigned char residual_SG_segment_count;
 771 /*23*/  unsigned char data_pointer[4] __attribute__ ((packed));
 772 /*26*/  unsigned char data_count[3];
 773 /*30*/  unsigned char host_scb[4] __attribute__ ((packed));
 774 /*31*/  u_char next_waiting;            /* Used to thread SCBs awaiting selection. */
 775 #define SCB_LIST_NULL 0x10              /* SCB list equivelent to NULL */
 776 #if 0
 777         /*
 778          *  No real point in transferring this to the
 779          *  SCB registers.
 780          */
 781         unsigned char RESERVED[1];
 782 #endif
 783 
 784         /*-----------------end of hardware supported fields----------------*/
 785         struct aic7xxx_scb *next;       /* next ptr when in free list */
 786         Scsi_Cmnd          *cmd;        /* Scsi_Cmnd for this scb */
 787         int                 state;      /* current state of scb */
 788 #define SCB_FREE               0x00
 789 #define SCB_ACTIVE             0x01
 790 #define SCB_ABORTED            0x02
 791 #define SCB_DEVICE_RESET       0x04
 792 #define SCB_IMMED              0x08
 793 #define SCB_SENSE              0x10
 794         unsigned int        position;       /* Position in scb array */
 795 #ifdef AIC7XXX_USE_SG
 796         struct scatterlist  sg;
 797         struct scatterlist  sense_sg;
 798 #endif
 799         unsigned char       sense_cmd[6];   /* Allocate 6 characters for sense command */
 800 };
 801 
 802 static struct {
 803   unsigned char errno;
 804   char *errmesg;
 805 } hard_error[] = {
 806   { ILLHADDR,  "Illegal Host Access" },
 807   { ILLSADDR,  "Illegal Sequencer Address referrenced" },
 808   { ILLOPCODE, "Illegal Opcode in sequencer program" },
 809   { PARERR,    "Sequencer Ram Parity Error" }
 810 };
 811 
 812 static unsigned char
 813 generic_sense[] = { REQUEST_SENSE, 0, 0, 0, 255, 0 };
 814 
 815 /*
 816  * The maximum number of SCBs we could have for ANY type
 817  * of card. DON'T FORGET TO CHANGE THE SCB MASK IN THE
 818  * SEQUENCER CODE IF THIS IS MODIFIED!
 819  */
 820 #define AIC7XXX_MAXSCB  16
 821 
 822 /*
 823  * Define a structure used for each host adapter, only one per IRQ.
 824  */
 825 struct aic7xxx_host {
 826   int                      base;             /* card base address */
 827   int                      maxscb;           /* hardware SCBs */
 828   int                      numscb;           /* current number of scbs */
 829   int                      extended;         /* extended xlate? */
 830   aha_type                 type;             /* card type */
 831   aha_bus_type             bus_type;         /* normal/twin/wide bus */
 832   unsigned char            a_scanned;        /* 0 not scanned, 1 scanned */
 833   unsigned char            b_scanned;        /* 0 not scanned, 1 scanned */
 834   unsigned int             isr_count;        /* Interrupt count */
 835   volatile unsigned char   unpause;          /* unpause value for HCNTRL */
 836   volatile unsigned char   pause;            /* pause value for HCNTRL */
 837   volatile unsigned short  needsdtr_copy;    /* default config */
 838   volatile unsigned short  needsdtr;
 839   volatile unsigned short  sdtr_pending;
 840   volatile unsigned short  needwdtr_copy;    /* default config */
 841   volatile unsigned short  needwdtr;
 842   volatile unsigned short  wdtr_pending;
 843   struct seeprom_config    seeprom;
 844   int                      have_seeprom;
 845   struct Scsi_Host        *next;             /* allow for multiple IRQs */
 846   struct aic7xxx_scb       scb_array[AIC7XXX_MAXSCB];  /* active commands */
 847   struct aic7xxx_scb      *free_scb;         /* list of free SCBs */
 848 };
 849 
 850 struct aic7xxx_host_config {
 851   int              irq;        /* IRQ number */
 852   int              base;       /* I/O base */
 853   int              maxscb;     /* hardware SCBs */
 854   int              unpause;    /* unpause value for HCNTRL */
 855   int              pause;      /* pause value for HCNTRL */
 856   int              scsi_id;    /* host SCSI ID */
 857   int              scsi_id_b;  /* host SCSI ID B channel for twin cards */
 858   int              extended;   /* extended xlate? */
 859   int              busrtime;   /* bus release time */
 860   aha_type         type;       /* card type */
 861   aha_bus_type     bus_type;   /* normal/twin/wide bus */
 862   aha_status_type  parity;     /* bus parity enabled/disabled */
 863   aha_status_type  low_term;   /* bus termination low byte */
 864   aha_status_type  high_term;  /* bus termination high byte (wide cards only) */
 865 };
 866 
 867 /*
 868  * Valid SCSIRATE values. (p. 3-17)
 869  * Provides a mapping of tranfer periods in ns to the proper value to
 870  * stick in the scsiscfr reg to use that transfer rate.
 871  */
 872 static struct {
 873   short period;
 874   short rate;
 875   char *english;
 876 } aic7xxx_syncrates[] = {
 877   { 100,   0,  "10.0" },
 878   { 125,   1,  "8.0"  },
 879   { 150,   2,  "6.67" },
 880   { 175,   3,  "5.7"  },
 881   { 200,   4,  "5.0"  },
 882   { 225,   5,  "4.4"  },
 883   { 250,   6,  "4.0"  },
 884   { 275,   7,  "3.6"  }
 885 };
 886 
 887 static int num_aic7xxx_syncrates =
 888     sizeof(aic7xxx_syncrates) / sizeof(aic7xxx_syncrates[0]);
 889 
 890 #ifdef AIC7XXX_DEBUG
 891 extern int vsprintf(char *, const char *, va_list);
 892 
 893 static void
 894 debug(const char *fmt, ...)
     /*  */
 895 {
 896   va_list ap;
 897   char buf[256];
 898 
 899   va_start(ap, fmt);
 900   vsprintf(buf, fmt, ap);
 901   printk(buf);
 902   va_end(ap);
 903 }
 904 
 905 static void
 906 debug_config(struct aic7xxx_host_config *p)
     /*  */
 907 {
 908   int host_conf, scsi_conf;
 909   unsigned char brelease;
 910   unsigned char dfthresh;
 911 
 912   static int DFT[] = { 0, 50, 75, 100 };
 913   static int SST[] = { 256, 128, 64, 32 };
 914   static char *BUSW[] = { "", "-TWIN", "-WIDE" };
 915 
 916   host_conf = inb(HA_HOSTCONF(p->base));
 917   scsi_conf = inb(HA_SCSICONF(p->base));
 918 
 919   /*
 920    * The 7870 gets the bus release time and data FIFO threshold
 921    * from the serial EEPROM (stored in the config structure) and
 922    * scsi_conf register respectively.  The 7770 gets the bus
 923    * release time and data FIFO threshold from the scsi_conf and
 924    * host_conf registers respectively.
 925    */
 926   if ((p->type == AIC_274x) || (p->type == AIC_284x))
 927   {
 928     brelease = scsi_conf & 0x3F;
 929     dfthresh = host_conf >> 6;
 930   }
 931   else
 932   {
 933     brelease = p->busrtime;
 934     dfthresh = scsi_conf >> 6;
 935   }
 936   if (brelease == 0)
 937   {
 938     brelease = 2;
 939   }
 940 
 941   switch (p->type)
 942   {
 943     case AIC_274x:
 944       printk("AIC7770%s AT EISA SLOT %d:\n", BUSW[p->bus_type], p->base >> 12);
 945       break;
 946 
 947     case AIC_284x:
 948       printk("AIC7770%s AT VLB SLOT %d:\n", BUSW[p->bus_type], p->base >> 12);
 949       break;
 950 
 951     case AIC_7870:
 952       printk("AIC7870%s (PCI-bus):\n", BUSW[p->bus_type]);
 953       break;
 954 
 955     case AIC_7850:
 956       printk("AIC7850%s (PCI-bus):\n", BUSW[p->bus_type]);
 957       break;
 958 
 959     case AIC_7872:
 960       printk("AIC7872%s (PCI-bus):\n", BUSW[p->bus_type]);
 961       break;
 962 
 963     default:
 964       panic("aic7xxx debug_config: internal error\n");
 965   }
 966 
 967   printk("    irq %d\n"
 968          "    bus release time %d bclks\n"
 969          "    data fifo threshold %d%%\n",
 970          p->irq,
 971          brelease,
 972          DFT[dfthresh]);
 973 
 974   printk("    SCSI CHANNEL A:\n"
 975          "        scsi id %d\n"
 976          "        scsi selection timeout %d ms\n"
 977          "        scsi bus reset at power-on %sabled\n",
 978          scsi_conf & 0x07,
 979          SST[(scsi_conf >> 3) & 0x03],
 980          (scsi_conf & 0x40) ? "en" : "dis");
 981 
 982   if (((p->type == AIC_274x) || (p->type == AIC_284x)) && p->parity == AIC_UNKNOWN)
 983   { /* Set the parity for 7770 based cards. */
 984     p->parity = (scsi_conf & 0x20) ? AIC_ENABLED : AIC_DISABLED;
 985   }
 986   if (p->parity != AIC_UNKNOWN)
 987   {
 988     printk("        scsi bus parity %sabled\n",
 989            (p->parity == AIC_ENABLED) ? "en" : "dis");
 990   }
 991 
 992   if (p->type == AIC_274x)
 993   {
 994     p->low_term = (scsi_conf & 0x80) ? AIC_ENABLED : AIC_DISABLED;
 995   }
 996   if (p->low_term != AIC_UNKNOWN)
 997   {
 998     printk("        scsi bus termination (low byte) %sabled\n",
 999           (p->low_term == AIC_ENABLED) ? "en" : "dis");
1000   }
1001   if ((p->bus_type == AIC_WIDE) && (p->high_term != AIC_UNKNOWN))
1002   {
1003     printk("        scsi bus termination (high byte) %sabled\n",
1004           (p->high_term == AIC_ENABLED) ? "en" : "dis");
1005   }
1006 }
1007 #else
1008 #  define debug(fmt, args...)
1009 #  define debug_config(x)
1010 #endif AIC7XXX_DEBUG
1011 
1012 /*
1013  * XXX - these options apply unilaterally to _all_ 274x/284x/294x
1014  *       cards in the system. This should be fixed, but then,
1015  *       does anyone really have more than one in a machine?
1016  */
1017 static int aic7xxx_extended = 0;        /* extended translation on? */
1018 static int aic7xxx_no_reset = 0;        /* no resetting of SCSI bus */
1019 
1020 /*+F*************************************************************************
1021  * Function:
1022  *   aic7xxx_setup
1023  *
1024  * Description:
1025  *   Handle Linux boot parameters.
1026  *-F*************************************************************************/
1027 void
1028 aic7xxx_setup(char *s, int *dummy)
     /*  */
1029 {
1030   int   i;
1031   char *p;
1032 
1033   static struct {
1034     char *name;
1035     int *flag;
1036   } options[] = {
1037     { "extended",    &aic7xxx_extended },
1038     { "no_reset",    &aic7xxx_no_reset },
1039     { NULL,          NULL}
1040   };
1041 
1042   for (p = strtok(s, ","); p; p = strtok(NULL, ","))
1043   {
1044     for (i = 0; options[i].name; i++)
1045     {
1046       if (!strcmp(options[i].name, p))
1047       {
1048         *(options[i].flag) = !0;
1049       }
1050     }
1051   }
1052 }
1053 
1054 /*+F*************************************************************************
1055  * Function:
1056  *   aic7xxx_loadseq
1057  *
1058  * Description:
1059  *   Load the sequencer code into the controller memory.
1060  *-F*************************************************************************/
1061 static void
1062 aic7xxx_loadseq(int base)
     /*  */
1063 {
1064   static unsigned char seqprog[] = {
1065     /*
1066      * Each sequencer instruction is 29 bits
1067      * long (fill in the excess with zeroes)
1068      * and has to be loaded from least -> most
1069      * significant byte, so this table has the
1070      * byte ordering reversed.
1071      */
1072 #   include "aic7xxx_seq.h"
1073   };
1074 
1075   /*
1076    * When the AIC-7770 is paused (as on chip reset), the
1077    * sequencer address can be altered and a sequencer
1078    * program can be loaded by writing it, byte by byte, to
1079    * the sequencer RAM port - the Adaptec documentation
1080    * recommends using REP OUTSB to do this, hence the inline
1081    * assembly. Since the address autoincrements as we load
1082    * the program, reset it back to zero afterward. Disable
1083    * sequencer RAM parity error detection while loading, and
1084    * make sure the LOADRAM bit is enabled for loading.
1085    */
1086   outb(PERRORDIS | SEQRESET | LOADRAM, SEQCTL(base));
1087 
1088   asm volatile("cld\n\t"
1089                "rep\n\t"
1090                "outsb"
1091                : /* no output */
1092                :"S" (seqprog), "c" (sizeof(seqprog)), "d" (SEQRAM(base))
1093                :"si", "cx", "dx");
1094 
1095   /*
1096    * WARNING!  This is a magic sequence!  After extensive
1097    * experimentation, it seems that you MUST turn off the
1098    * LOADRAM bit before you play with SEQADDR again, else
1099    * you will end up with parity errors being flagged on
1100    * your sequencer program. (You would also think that
1101    * turning off LOADRAM and setting SEQRESET to reset the
1102    * address to zero would work, but you need to do it twice
1103    * for it to take effect on the address. Timing problem?)
1104    */
1105   do {
1106     /*
1107      * Actually, reset it until
1108      * the address shows up as
1109      * zero just to be safe..
1110      */
1111     outb(SEQRESET | FASTMODE, SEQCTL(base));
1112   } while ((inb(SEQADDR0(base)) != 0) && (inb(SEQADDR1(base)) != 0));
1113 }
1114 
1115 /*+F*************************************************************************
1116  * Function:
1117  *   aic7xxx_delay
1118  *
1119  * Description:
1120  *   Delay for specified amount of time.
1121  *-F*************************************************************************/
1122 static void
1123 aic7xxx_delay(int seconds)
     /*  */
1124 {
1125   unsigned long i;
1126 
1127   i = jiffies + (seconds * 100);  /* compute time to stop */
1128 
1129   while (jiffies < i)
1130   {
1131     ;  /* Do nothing! */
1132   }
1133 }
1134 
1135 /*+F*************************************************************************
1136  * Function:
1137  *   rcs_version
1138  *
1139  * Description:
1140  *   Return a string containing just the RCS version number from either
1141  *   an Id or Revison RCS clause.
1142  *-F*************************************************************************/
1143 const char *
1144 rcs_version(const char *version_info)
     /*  */
1145 {
1146   static char buf[10];
1147   char *bp, *ep;
1148 
1149   bp = NULL;
1150   strcpy(buf, "????");
1151   if (!strncmp(version_info, "$Id: ", 5))
1152   {
1153     if ((bp = strchr(version_info, ' ')) != NULL)
1154     {
1155       bp++;
1156       if ((bp = strchr(bp, ' ')) != NULL)
1157       {
1158         bp++;
1159       }
1160     }
1161   }
1162   else
1163   {
1164     if (!strncmp(version_info, "$Revision: ", 11))
1165     {
1166       if ((bp = strchr(version_info, ' ')) != NULL)
1167       {
1168         bp++;
1169       }
1170     }
1171   }
1172 
1173   if (bp != NULL)
1174   {
1175     if ((ep = strchr(bp, ' ')) != NULL)
1176     {
1177       register int len = ep - bp;
1178 
1179       strncpy(buf, bp, len);
1180       buf[len] = '\0';
1181     }
1182   }
1183 
1184   return buf;
1185 }
1186 
1187 /*+F*************************************************************************
1188  * Function:
1189  *   aic7xxx_info
1190  *
1191  * Description:
1192  *   Return a string describing the driver.
1193  *-F*************************************************************************/
1194 const char *
1195 aic7xxx_info(struct Scsi_Host *notused)
     /*  */
1196 {
1197   static char buffer[128];
1198 
1199   strcpy(buffer, "Adaptec AHA274x/284x/294x (EISA/VLB/PCI-Fast SCSI) ");
1200   strcat(buffer, rcs_version(AIC7XXX_C_VERSION));
1201   strcat(buffer, "/");
1202   strcat(buffer, rcs_version(AIC7XXX_H_VERSION));
1203   strcat(buffer, "/");
1204   strcat(buffer, rcs_version(AIC7XXX_SEQ_VER));
1205 
1206   return buffer;
1207 }
1208 
1209 /*+F*************************************************************************
1210  * Function:
1211  *   aic7xxx_putscb
1212  *
1213  * Description:
1214  *   Transfer a SCB to the controller.
1215  *-F*************************************************************************/
1216 static void
1217 aic7xxx_putscb(int base, struct aic7xxx_scb *scb)
     /*  */
1218 {
1219 #ifdef AIC7XXX_USE_DMA
1220   /*
1221    * All we need to do, is to output the position
1222    * of the SCB in the SCBARRAY to the QINFIFO
1223    * of the host adapter.
1224    */
1225   outb(scb->position, QINFIFO(base));
1226 #else
1227   /*
1228    * By turning on the SCB auto increment, any reference
1229    * to the SCB I/O space postincrements the SCB address
1230    * we're looking at. So turn this on and dump the relevant
1231    * portion of the SCB to the card.
1232    */
1233   outb(SCBAUTO, SCBCNT(base));
1234 
1235   asm volatile("cld\n\t"
1236                "rep\n\t"
1237                "outsb"
1238                : /* no output */
1239                :"S" (scb), "c" (SCB_DOWNLOAD_SIZE), "d" (SCBARRAY(base))
1240                :"si", "cx", "dx");
1241 
1242   outb(0, SCBCNT(base));
1243 #endif
1244 }
1245 
1246 /*+F*************************************************************************
1247  * Function:
1248  *   aic7xxx_putdmascb
1249  *
1250  * Description:
1251  *   DMA a SCB to the controller.
1252  *-F*************************************************************************/
1253 static void
1254 aic7xxx_putdmascb(int base, struct aic7xxx_scb *scb)
     /*  */
1255 {
1256   /*
1257    * By turning on the SCB auto increment, any reference
1258    * to the SCB I/O space postincrements the SCB address
1259    * we're looking at. So turn this on and dump the relevant
1260    * portion of the SCB to the card.
1261    */
1262   outb(SCBAUTO, SCBCNT(base));
1263 
1264   asm volatile("cld\n\t"
1265                "rep\n\t"
1266                "outsb"
1267                : /* no output */
1268                :"S" (scb), "c" (31), "d" (SCBARRAY(base))
1269                :"si", "cx", "dx");
1270 
1271   outb(0, SCBCNT(base));
1272 }
1273 
1274 /*+F*************************************************************************
1275  * Function:
1276  *   aic7xxx_getscb
1277  *
1278  * Description:
1279  *   Get a SCB from the controller.
1280  *-F*************************************************************************/
1281 static void
1282 aic7xxx_getscb(int base, struct aic7xxx_scb *scb)
     /*  */
1283 {
1284   /*
1285    * This is almost identical to aic7xxx_putscb().
1286    */
1287   outb(SCBAUTO, SCBCNT(base));
1288 
1289   asm volatile("cld\n\t"
1290                "rep\n\t"
1291                "insb"
1292                : /* no output */
1293                :"D" (scb), "c" (SCB_UPLOAD_SIZE), "d" (SCBARRAY(base))
1294                :"di", "cx", "dx");
1295 
1296   outb(0, SCBCNT(base));
1297 }
1298 
1299 /*+F*************************************************************************
1300  * Function:
1301  *   aic7xxx_length
1302  *
1303  * Description:
1304  *   How much data should be transferred for this SCSI command? Stop
1305  *   at segment sg_last if it's a scatter-gather command so we can
1306  *   compute underflow easily.
1307  *-F*************************************************************************/
1308 static unsigned
1309 aic7xxx_length(Scsi_Cmnd *cmd, int sg_last)
     /*  */
1310 {
1311   int i, segments;
1312   unsigned length;
1313   struct scatterlist *sg;
1314 
1315   segments = cmd->use_sg - sg_last;
1316   sg = (struct scatterlist *) cmd->buffer;
1317 
1318   if (cmd->use_sg)
1319   {
1320     for (i = length = 0; i < cmd->use_sg && i < segments; i++)
1321     {
1322       length += sg[i].length;
1323     }
1324   }
1325   else
1326   {
1327     length = cmd->request_bufflen;
1328   }
1329 
1330   return(length);
1331 }
1332 
1333 /*+F*************************************************************************
1334  * Function:
1335  *   aic7xxx_scsirate
1336  *
1337  * Description:
1338  *   Look up the valid period to SCSIRATE conversion in our table
1339  *-F*************************************************************************/
1340 static void
1341 aic7xxx_scsirate(unsigned char *scsirate, unsigned char period,
     /*  */
1342                  unsigned char offset, int target)
1343 {
1344   int i;
1345 
1346   for (i = 0; i < num_aic7xxx_syncrates; i++)
1347   {
1348     if ((aic7xxx_syncrates[i].period - period) >= 0)
1349     {
1350       *scsirate = (aic7xxx_syncrates[i].rate << 4) | (offset & 0x0F);
1351       printk("aic7xxx: target %d now synchronous at %sMb/s, offset = 0x%x\n",
1352              target, aic7xxx_syncrates[i].english, offset);
1353       return;
1354     }
1355   }
1356 
1357   /*
1358    * Default to asyncronous transfer
1359    */
1360   *scsirate = 0;
1361   printk("aic7xxx: target %d using asynchronous transfers\n", target);
1362 }
1363 
1364 /*+F*************************************************************************
1365  * Function:
1366  *   aic7xxx_isr
1367  *
1368  * Description:
1369  *   SCSI controller interrupt handler.
1370  *
1371  *   NOTE: Since we declared this using SA_INTERRUPT, interrupts should
1372  *         be disabled all through this function unless we say otherwise.
1373  *-F*************************************************************************/
1374 static void
1375 aic7xxx_isr(int irq, struct pt_regs * regs)
     /*  */
1376 {
1377   int base, intstat;
1378   struct aic7xxx_host *p;
1379   struct aic7xxx_scb *scb;
1380   unsigned char active, ha_flags, transfer;
1381   unsigned char scsi_id, bus_width;
1382   unsigned char offset, rate, scratch;
1383   unsigned char max_offset;
1384   unsigned char head, tail;
1385   unsigned short target_mask;
1386   long flags;
1387   void *addr;
1388   int actual;
1389   int target, tcl;
1390   int scbptr;
1391   Scsi_Cmnd *cmd;
1392 #if 0
1393 static int_count = 0;
1394 #endif
1395 
1396   p = (struct aic7xxx_host *) aic7xxx_boards[irq]->hostdata;
1397 #ifdef AIC7XXX_SHARE_IRQS
1398   /*
1399    * Search for the host with a pending interrupt.
1400    */
1401   while ((p != NULL) && !(inb(INTSTAT(p->base)) & INT_PEND))
1402   {
1403     p = (struct aic7xxx_host *) p->next->hostdata;
1404   }
1405   if (p == NULL)
1406   {
1407     printk("aic7xxx_isr: Encountered spurious interrupt.\n");
1408     return;
1409   }
1410 #endif
1411   base = p->base;
1412   if (p->isr_count == 0xffffffff)
1413   {
1414     p->isr_count = 0;
1415   }
1416   else
1417   {
1418     p->isr_count = p->isr_count + 1;
1419   }
1420   if ((p->a_scanned == 0) && (p->isr_count == 1))
1421   {
1422     /* Allow for one interrupt when the card is enabled. */
1423     return;
1424   }
1425 
1426   /*
1427    * Handle all the interrupt sources - especially for SCSI
1428    * interrupts, we won't get a second chance at them.
1429    */
1430   intstat = inb(INTSTAT(base));
1431 
1432   if (intstat & BRKADRINT)
1433   {
1434     int i;
1435     unsigned char errno = inb(ERROR(base));
1436 
1437     printk("aic7xxx_isr: brkadrint (0x%x):\n", errno);
1438     for (i = 0; i < NUMBER(hard_error); i++)
1439     {
1440       if (errno & hard_error[i].errno)
1441       {
1442         printk("  %s\n", hard_error[i].errmesg);
1443       }
1444     }
1445 
1446     panic("aic7xxx_isr: brkadrint, error = 0x%x, seqaddr = 0x%x\n",
1447           inb(ERROR(base)),
1448           inb(SEQADDR1(base)) << 8 | inb(SEQADDR0(base)));
1449   }
1450 
1451   if (intstat & SEQINT)
1452   {
1453     /*
1454      * Although the sequencer is paused immediately on
1455      * a SEQINT, an interrupt for a SCSIINT or a CMDCMPLT
1456      * condition will have unpaused the sequencer before
1457      * this point.
1458      */
1459     PAUSE_SEQUENCER(p);
1460 
1461     switch (intstat & SEQINT_MASK)
1462     {
1463       case BAD_PHASE:
1464         panic("aic7xxx_isr: unknown scsi bus phase\n");
1465 
1466       case SEND_REJECT:
1467         debug("aic7xxx_isr warning: issuing message reject, 1st byte 0x%x\n",
1468               inb(HA_REJBYTE(base)));
1469         break;
1470 
1471       case NO_IDENT:
1472         panic("aic7xxx_isr: reconnecting target %d at seqaddr 0x%x "
1473               "didn't issue IDENTIFY message\n",
1474               (inb(SELID(base)) >> 4) & 0x0F,
1475               (inb(SEQADDR1(base)) << 8) | inb(SEQADDR0(base)));
1476         break;
1477 
1478       case NO_MATCH:
1479         tcl = inb(SCBARRAY(base) + 1);
1480         target = (tcl >> 4) & 0x0F;
1481         /* Purposefully mask off the top bit of targets 8-15. */
1482         target_mask = 0x01 << (target & 0x07);
1483 
1484         debug("aic7xxx_isr: sequencer couldn't find match "
1485               "for reconnecting target %d, channel %d, lun %d - "
1486               "issuing ABORT\n", target, (tcl & 0x08) >> 3, tcl & 0x07);
1487         if (tcl & 0x88)
1488         {
1489           /* Second channel stores its info in byte
1490            * two of HA_ACTIVE
1491            */
1492           active = inb(HA_ACTIVE1(base));
1493           active = active & ~(target_mask);
1494           outb(active, HA_ACTIVE1(base));
1495         }
1496         else
1497         {
1498           active = inb(HA_ACTIVE0(base));
1499           active = active & ~(target_mask);
1500           outb(active, HA_ACTIVE0(base));
1501         }
1502 #ifdef AIC7XXX_USE_DMA
1503         outb(SCB_NEEDDMA, SCBARRAY(base));
1504 #endif
1505 
1506         /*
1507          * Check out why this use to be outb(0x80, CLRINT(base))
1508          * clear the timeout
1509          */
1510         outb(CLRSELTIMEO, CLRSINT1(base));
1511         RESTART_SEQUENCER(p);
1512         break;
1513 
1514       case MSG_SDTR:
1515         /*
1516          * Help the sequencer to translate the negotiated
1517          * transfer rate. Transfer is 1/4 the period
1518          * in ns as is returned by the sync negotiation
1519          * message. So, we must multiply by four.
1520          */
1521         transfer = (inb(HA_ARG_1(base)) << 2);
1522         offset = inb(ACCUM(base));
1523         scsi_id = inb(SCSIID(base)) >> 0x04;
1524         if (inb(SBLKCTL(base)) & 0x08)
1525         {
1526           scsi_id = scsi_id + 8;  /* B channel */
1527         }
1528         target_mask = (0x01 << scsi_id);
1529         scratch = inb(HA_TARG_SCRATCH(base) + scsi_id);
1530         /*
1531          * The maximum offset for a wide device is 0x08; for a
1532          * 8-bit bus device the maximum offset is 0x0f.
1533          */
1534         if (scratch & 0x80)
1535         {
1536           max_offset = 0x08;
1537         }
1538         else
1539         {
1540           max_offset = 0x0f;
1541         }
1542         aic7xxx_scsirate(&rate, transfer, MIN(offset, max_offset), scsi_id);
1543         /*
1544          * Preserve the wide transfer flag.
1545          */
1546         rate = rate | (scratch & 0x80);
1547         outb(rate, HA_TARG_SCRATCH(base) + scsi_id);
1548         outb(rate, SCSIRATE(base));
1549         if ((rate & 0xf) == 0)
1550         { /*
1551            * The requested rate was so low that asynchronous transfers
1552            * are faster (not to mention the controller won't support
1553            * them), so we issue a reject to ensure we go to asynchronous
1554            * transfers.
1555            */
1556            outb(SEND_REJ, HA_RETURN_1(base));
1557         }
1558         else
1559         {
1560           /*
1561            * See if we initiated Sync Negotiation
1562            */
1563           if (p->sdtr_pending & target_mask)
1564           {
1565             /*
1566              * Don't send an SDTR back to the target.
1567              */
1568             outb(0, HA_RETURN_1(base));
1569           }
1570           else
1571           {
1572             /*
1573              * Send our own SDTR in reply.
1574              */
1575             printk("Sending SDTR!!\n");
1576             outb(SEND_SDTR, HA_RETURN_1(base));
1577           }
1578         }
1579         /*
1580          * Clear the flags.
1581          */
1582         p->needsdtr = p->needsdtr & ~target_mask;
1583         p->sdtr_pending = p->sdtr_pending & ~target_mask;
1584         break;
1585 
1586       case MSG_WDTR:
1587       {
1588         bus_width = inb(ACCUM(base));
1589         scsi_id = inb(SCSIID(base)) >> 0x04;
1590         if (inb(SBLKCTL(base)) & 0x08)
1591         {
1592           scsi_id = scsi_id + 8;  /* B channel */
1593         }
1594         printk("Received MSG_WDTR, scsi_id = %d, "
1595                "needwdtr = 0x%x\n", scsi_id, p->needwdtr);
1596         scratch = inb(HA_TARG_SCRATCH(base) + scsi_id);
1597 
1598         target_mask = (0x01 << scsi_id);
1599         if (p->wdtr_pending & target_mask)
1600         {
1601           /*
1602            * Don't send an WDTR back to the target, since we asked first.
1603            */
1604           outb(0, HA_RETURN_1(base));
1605           switch (bus_width)
1606           {
1607             case BUS_8_BIT:
1608               scratch = scratch & 0x7F;
1609               break;
1610 
1611             case BUS_16_BIT:
1612               printk("aic7xxx_isr: target %d using 16 bit transfers\n",
1613                      scsi_id);
1614               scratch = scratch | 0x80;
1615               break;
1616           }
1617         }
1618         else
1619         {
1620           /*
1621            * Send our own WDTR in reply.
1622            */
1623           printk("Will send WDTR!!\n");
1624           switch (bus_width)
1625           {
1626             case BUS_8_BIT:
1627               scratch = scratch & 0x7F;
1628               break;
1629 
1630             case BUS_32_BIT:
1631               /* Negotiate 16 bits. */
1632               bus_width = BUS_16_BIT;
1633               /* Yes, we mean to fall thru here */
1634 
1635             case BUS_16_BIT:
1636               printk("aic7xxx_isr: target %d using 16 bit transfers\n",
1637                      scsi_id);
1638               scratch = scratch | 0x80;
1639               break;
1640           }
1641           outb(bus_width | SEND_WDTR, HA_RETURN_1(base));
1642         }
1643         p->needwdtr = p->needwdtr & ~target_mask;
1644         p->wdtr_pending = p->wdtr_pending & ~target_mask;
1645         outb(scratch, HA_TARG_SCRATCH(base) + scsi_id);
1646         outb(scratch, SCSIRATE(base));
1647         break;
1648       }
1649 
1650       case MSG_REJECT:
1651       {
1652         /*
1653          * What we care about here is if we had an
1654          * outstanding SDTR or WDTR message for this
1655          * target. If we did, this is a signal that
1656          * the target is refusing negotiation.
1657          */
1658 
1659         unsigned char targ_scratch, scsi_id;
1660         unsigned short mask;
1661 
1662         scsi_id = inb(SCSIID(base)) >> 0x04;
1663         if (inb(SBLKCTL(base)) & 0x08)
1664         {
1665           scsi_id = scsi_id + 8;
1666         }
1667 
1668         mask = (0x01 << scsi_id);
1669 
1670         targ_scratch = inb(HA_TARG_SCRATCH(base) + scsi_id);
1671 
1672         if (p->wdtr_pending & mask)
1673         {
1674           /*
1675            * note 8bit xfers and clear flag
1676            */
1677           targ_scratch = targ_scratch & 0x7F;
1678           p->needwdtr = p->needwdtr & ~mask;
1679           p->wdtr_pending = p->wdtr_pending & ~mask;
1680           outb(targ_scratch, HA_TARG_SCRATCH(base) + scsi_id);
1681           printk("aic7xxx: target %d refusing WIDE negotiation. Using "
1682                  "8 bit transfers\n", scsi_id);
1683         }
1684         else
1685         {
1686           if (p->sdtr_pending & mask)
1687           {
1688             /*
1689              * note asynch xfers and clear flag
1690              */
1691             targ_scratch = targ_scratch & 0xF0;
1692             p->needsdtr = p->needsdtr & ~mask;
1693             p->sdtr_pending = p->sdtr_pending & ~mask;
1694             outb(targ_scratch, HA_TARG_SCRATCH(base) + scsi_id);
1695             printk("aic7xxx: target %d refusing syncronous negotiation. Using "
1696                    "asyncronous transfers\n", scsi_id);
1697           }
1698           /*
1699            * Otherwise, we ignore it.
1700            */
1701         }
1702         outb(targ_scratch, HA_TARG_SCRATCH(base) + scsi_id);
1703         outb(targ_scratch, SCSIRATE(base));
1704         break;
1705       }
1706 
1707       case BAD_STATUS:
1708         scsi_id = inb(SCSIID(base)) >> 0x04;
1709         scbptr = inb(SCBPTR(base));
1710         scb = &(p->scb_array[scbptr]);
1711         outb(0, HA_RETURN_1(base));   /* CHECK_CONDITION may change this */
1712         if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
1713         {
1714           printk("aic7xxx_isr: referenced scb not valid "
1715                  "during seqint 0x%x scb(%d) state(%x), cmd(%x)\n",
1716                  intstat, scbptr, scb->state, (unsigned int) scb->cmd);
1717         }
1718         else
1719         {
1720           cmd = scb->cmd;
1721           aic7xxx_getscb(base, scb);
1722           aic7xxx_status(cmd) = scb->target_status;
1723 
1724           cmd->result = cmd->result | scb->target_status;
1725 
1726           /*
1727            * This test is just here for debugging purposes.
1728            * It will go away when the timeout problem is resolved.
1729            */
1730           switch (status_byte(scb->target_status))
1731           {
1732             case GOOD:
1733               break;
1734 
1735             case CHECK_CONDITION:
1736               if ((aic7xxx_error(cmd) == 0) && !(cmd->flags & WAS_SENSE))
1737               {
1738                 void         *req_buf;
1739 #ifndef AIC7XXX_USE_SG
1740                 unsigned int  req_buflen;
1741 #endif
1742 
1743                 /* Update the timeout for the SCSI command. */
1744 /*                update_timeout(cmd, SENSE_TIMEOUT); */
1745 
1746                 /* Send a sense command to the requesting target. */
1747                 cmd->flags = cmd->flags | WAS_SENSE;
1748                 memcpy((void *) scb->sense_cmd, (void *) generic_sense,
1749                        sizeof(generic_sense));
1750 
1751                 scb->sense_cmd[1] = cmd->lun << 5;
1752                 scb->sense_cmd[4] = sizeof(cmd->sense_buffer);
1753 
1754 #ifdef AIC7XXX_USE_SG
1755                 scb->sense_sg.address = (char *) &cmd->sense_buffer;
1756                 scb->sense_sg.length = sizeof(cmd->sense_buffer);
1757                 req_buf = &scb->sense_sg;
1758 #else
1759                 req_buf = &cmd->sense_buffer;
1760                 req_buflen = sizeof(cmd->sense_buffer);
1761 #endif
1762                 cmd->cmd_len = COMMAND_SIZE(cmd->cmnd[0]);
1763                 memset(scb, 0, SCB_DOWNLOAD_SIZE);
1764                 scb->target_channel_lun = ((cmd->target << 4) & 0xF0) |
1765                     ((cmd->channel & 0x01) << 3) | (cmd->lun & 0x07);
1766                 addr = scb->sense_cmd;
1767                 scb->SCSI_cmd_length = COMMAND_SIZE(scb->sense_cmd[0]);
1768                 memcpy(scb->SCSI_cmd_pointer, &addr,
1769                        sizeof(scb->SCSI_cmd_pointer));
1770 #ifdef AIC7XXX_USE_SG
1771                 scb->SG_segment_count = 1;
1772                 memcpy (scb->SG_list_pointer, &req_buf,
1773                         sizeof(scb->SG_list_pointer));
1774 #else
1775                 scb->SG_segment_count = 0;
1776                 memcpy (scb->data_pointer, &req_buf,
1777                         sizeof(scb->data_pointer));
1778                 memcpy (scb->data_count, &req_buflen, 3);
1779 #endif
1780 
1781                 outb(SCBAUTO, SCBCNT(base));
1782                 asm volatile("cld\n\t"
1783                              "rep\n\t"
1784                              "outsb"
1785                              : /* no output */
1786                              :"S" (scb), "c" (SCB_DOWNLOAD_SIZE), "d" (SCBARRAY(base))
1787                              :"si", "cx", "dx");
1788                 outb(0, SCBCNT(base));
1789                 outb(SCB_LIST_NULL, (SCBARRAY(base) + 30));
1790 
1791                 /*
1792                  * Add this SCB to the "waiting for selection" list.
1793                  */
1794                 head = inb(WAITING_SCBH(base));
1795                 tail = inb(WAITING_SCBT(base));
1796                 if (head & SCB_LIST_NULL)
1797                 { /* list is empty */
1798                   head = scb->position;
1799                   tail = SCB_LIST_NULL;
1800                 }
1801                 else
1802                 {
1803                   if (tail & SCB_LIST_NULL)
1804                   { /* list has one element */
1805                     tail = scb->position;
1806                     outb(head, SCBPTR(base));
1807                     outb(tail, (SCBARRAY(base) + 30));
1808                   }
1809                   else
1810                   { /* list has more than one element */
1811                     outb(tail, SCBPTR(base));
1812                     tail = scb->position;
1813                     outb(tail, (SCBARRAY(base) + 30));
1814                   }
1815                 }
1816                 outb(head, WAITING_SCBH(base));
1817                 outb(tail, WAITING_SCBT(base));
1818                 outb(SEND_SENSE, HA_RETURN_1(base));
1819               }  /* first time sense, no errors */
1820               else
1821               {
1822                 /*
1823                  * Indicate that we asked for sense, have the sequencer do
1824                  * a normal command complete, and have the scsi driver handle
1825                  * this condition.
1826                  */
1827                 cmd->flags = cmd->flags | ASKED_FOR_SENSE;
1828               }
1829               break;
1830 
1831             case BUSY:
1832               printk("aic7xxx_isr: Target busy\n");
1833               if (!aic7xxx_error(cmd))
1834               {
1835                 aic7xxx_error(cmd) = DID_BUS_BUSY;
1836               }
1837               break;
1838 
1839             case QUEUE_FULL:
1840               printk("aic7xxx_isr: Queue full\n");
1841               if (!aic7xxx_error(cmd))
1842               {
1843                 aic7xxx_error(cmd) = DID_RETRY_COMMAND;
1844               }
1845               break;
1846 
1847             default:
1848               printk("aic7xxx_isr: Unexpected target status 0x%x\n",
1849                      scb->target_status);
1850               if (!aic7xxx_error(cmd))
1851               {
1852                 aic7xxx_error(cmd) = DID_RETRY_COMMAND;
1853               }
1854               break;
1855           }  /* end switch */
1856         }  /* end else of */
1857         break;
1858 
1859       case RESIDUAL:
1860         scbptr = inb(SCBPTR(base));
1861         scb = &(p->scb_array[scbptr]);
1862         if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
1863         {
1864           printk("aic7xxx_isr: referenced scb not valid "
1865                  "during seqint 0x%x scb(%d) state(%x), cmd(%x)\n",
1866                  intstat, scbptr, scb->state, (unsigned int) scb->cmd);
1867         }
1868         else
1869         {
1870           cmd = scb->cmd;
1871           /*
1872            *  Don't destroy valid residual information with
1873            *  residual coming from a check sense operation.
1874            */
1875           if (!(cmd->flags & WAS_SENSE))
1876           {
1877             /*
1878              *  We had an underflow. At this time, there's only
1879              *  one other driver that bothers to check for this,
1880              *  and cmd->underflow seems to be set rather half-
1881              *  heartedly in the higher-level SCSI code.
1882              */
1883             actual = aic7xxx_length(cmd, scb->residual_SG_segment_count);
1884 
1885             actual -= ((inb(SCBARRAY(base + 17)) << 16) |
1886                        (inb(SCBARRAY(base + 16)) <<  8) |
1887                        inb(SCBARRAY(base + 15)));
1888 
1889             if (actual < cmd->underflow)
1890             {
1891               printk("aic7xxx: target %d underflow - "
1892                      "wanted (at least) %u, got %u\n",
1893                      cmd->target, cmd->underflow, actual);
1894 
1895               aic7xxx_error(cmd) = DID_RETRY_COMMAND;
1896               aic7xxx_status(cmd) = scb->target_status;
1897             }
1898           }
1899         }
1900         break;
1901 
1902       case ABORT_TAG:
1903         scbptr = inb(SCBPTR(base));
1904         scb = &(p->scb_array[scbptr]);
1905         if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
1906         {
1907           printk("aic7xxx_isr: referenced scb not valid "
1908                  "during seqint 0x%x scb(%d) state(%x), cmd(%x)\n",
1909                  intstat, scbptr, scb->state, (unsigned int) scb->cmd);
1910         }
1911         else
1912         {
1913           cmd = scb->cmd;
1914           /*
1915            * We didn't recieve a valid tag back from the target
1916            * on a reconnect.
1917            */
1918           printk("aic7xxx_isr: invalid tag recieved on channel %c "
1919                  "target %d, lun %d -- sending ABORT_TAG\n",
1920                   (cmd->channel & 0x01) ? 'B':'A',
1921                   cmd->target, cmd->lun & 0x07);
1922           /*
1923            *  This is a critical section, since we don't want the
1924            *  queue routine mucking with the host data.
1925            */
1926           save_flags(flags);
1927           cli();
1928 
1929           /*
1930            *  Process the command after marking the scb as free
1931            *  and adding it to the free list.
1932            */
1933           scb->state = SCB_FREE;
1934           scb->cmd = NULL;
1935           scb->next = p->free_scb;      /* preserve next pointer */
1936           p->free_scb = scb;            /* add at head of list */
1937 
1938           restore_flags (flags);
1939           cmd->result = (DID_RETRY_COMMAND << 16);
1940           cmd->scsi_done(cmd);
1941         }
1942         break;
1943 
1944       case AWAITING_MSG:
1945         scbptr = inb(SCBPTR(base));
1946         scb = &(p->scb_array[scbptr]);
1947         if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
1948         {
1949           printk("aic7xxx_isr: referenced scb not valid "
1950                  "during seqint 0x%x scb(%d) state(%x), cmd(%x)\n",
1951                  intstat, scbptr, scb->state, (unsigned int) scb->cmd);
1952         }
1953         else
1954         {
1955           /*
1956            * This SCB had a zero length command, informing the sequencer
1957            * that we wanted to send a special message to this target.
1958            * We only do this for BUS_DEVICE_RESET messages currently.
1959            */
1960            if (scb->state & SCB_DEVICE_RESET)
1961            {
1962              outb(MSG_BUS_DEVICE_RESET, HA_MSG_START(base));
1963              outb(1, HA_MSG_LEN(base));
1964            }
1965            else
1966            {
1967              panic ("aic7xxx_isr: AWAITING_SCB for an SCB that does "
1968                     "not have a waiting message");
1969            }
1970         }
1971         break;
1972 
1973       default:               /* unknown */
1974         debug("aic7xxx_isr: seqint, intstat = 0x%x, scsisigi = 0x%x\n",
1975               intstat, inb(SCSISIGI(base)));
1976         break;
1977     }
1978     outb(CLRSEQINT, CLRINT(base));
1979     UNPAUSE_SEQUENCER(p);
1980   }
1981 
1982   if (intstat & SCSIINT)
1983   {
1984     int status = inb(SSTAT1(base));
1985 
1986     scbptr = inb(SCBPTR(base));
1987     scb = &p->scb_array[scbptr];
1988     if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
1989     {
1990       printk("aic7xxx_isr: no command for scb (scsiint)\n");
1991       /*
1992        * Turn off the interrupt and set status
1993        * to zero, so that it falls through the
1994        * reset of the SCSIINT code.
1995        */
1996       outb(status, CLRSINT1(base));
1997       UNPAUSE_SEQUENCER(p);
1998       outb(CLRSCSIINT, CLRINT(base));
1999       status = 0;
2000       scb = NULL;
2001     }
2002     else
2003     {
2004       cmd = scb->cmd;
2005 
2006       /*
2007        * Only the SCSI Status 1 register has information
2008        * about exceptional conditions that we'd have a
2009        * SCSIINT about; anything in SSTAT0 will be handled
2010        * by the sequencer. Note that there can be multiple
2011        * bits set.
2012        */
2013       if (status & SELTO)
2014       {
2015         unsigned char target_mask = (1 << (cmd->target & 0x07));
2016         unsigned char waiting;
2017 
2018         /*
2019          * Hardware selection timer has expired. Turn
2020          * off SCSI selection sequence.
2021          */
2022         outb(ENRSELI, SCSISEQ(base));
2023         cmd->result = (DID_TIME_OUT << 16);
2024         /*
2025          * Clear an pending messages for the timed out
2026          * target and mark the target as free.
2027          */
2028         ha_flags = inb(HA_FLAGS(base));
2029         outb(ha_flags & ~ACTIVE_MSG, HA_FLAGS(base));
2030 
2031         if (scb->target_channel_lun & 0x88)
2032         {
2033           active = inb(HA_ACTIVE1(base));
2034           active = active & ~(target_mask);
2035           outb(active, HA_ACTIVE1(base));
2036         }
2037         else
2038         {
2039           active = inb(HA_ACTIVE0(base));
2040           active = active & ~(target_mask);
2041           outb(active, HA_ACTIVE0(base));
2042         }
2043 
2044 #ifdef AIC7XXX_USE_DMA
2045         outb(SCB_NEEDDMA, SCBARRAY(base));
2046 #endif
2047 
2048         /*
2049          * Shut off the offending interrupt sources, reset
2050          * the sequencer address to zero and unpause it,
2051          * then call the high-level SCSI completion routine.
2052          *
2053          * WARNING!  This is a magic sequence!  After many
2054          * hours of guesswork, turning off the SCSI interrupts
2055          * in CLRSINT? does NOT clear the SCSIINT bit in
2056          * INTSTAT. By writing to the (undocumented, unused
2057          * according to the AIC-7770 manual) third bit of
2058          * CLRINT, you can clear INTSTAT. But, if you do it
2059          * while the sequencer is paused, you get a BRKADRINT
2060          * with an Illegal Host Address status, so the
2061          * sequencer has to be restarted first.
2062          */
2063         outb(CLRSELTIMEO, CLRSINT1(base));
2064 
2065         outb(CLRSCSIINT, CLRINT(base));
2066 
2067         /* Shift the waiting for selection queue forward */
2068         waiting = inb(WAITING_SCBH(base));
2069         outb(waiting, SCBPTR(base));
2070         waiting = inb(SCBARRAY(base) + 30);
2071         outb(waiting, WAITING_SCBH(base));
2072 
2073         RESTART_SEQUENCER(p);
2074         /*
2075          * This is a critical section, since we don't want the
2076          * queue routine mucking with the host data.
2077          */
2078         save_flags(flags);
2079         cli();
2080 
2081         /*
2082          * Process the command after marking the scb as free
2083          * and adding it to the free list.
2084          */
2085         scb->state = SCB_FREE;
2086         scb->cmd = NULL;
2087         scb->next = p->free_scb;        /* preserve next pointer */
2088         p->free_scb = scb;              /* add at head of list */
2089 
2090         restore_flags(flags);
2091 
2092         cmd->scsi_done(cmd);
2093 #if 0
2094   printk("aic7xxx_isr: SELTO scb(%d) state(%x), cmd(%x)\n",
2095          scb->position, scb->state, (unsigned int) scb->cmd);
2096 #endif
2097       }
2098       else
2099       {
2100         if (status & SCSIPERR)
2101         {
2102           /*
2103            * A parity error has occurred during a data
2104            * transfer phase. Flag it and continue.
2105            */
2106           printk("aic7xxx: parity error on target %d, "
2107                  "channel %d, lun %d\n",
2108                  cmd->target,
2109                  cmd->channel & 0x01,
2110                  cmd->lun & 0x07);
2111           aic7xxx_error(cmd) = DID_PARITY;
2112 
2113           /*
2114            * Clear interrupt and resume as above.
2115            */
2116           outb(CLRSCSIPERR, CLRSINT1(base));
2117           UNPAUSE_SEQUENCER(p);
2118 
2119           outb(CLRSCSIINT, CLRINT(base));
2120           scb = NULL;
2121         }
2122         else
2123         {
2124           if (! (status & BUSFREE))
2125           {
2126              /*
2127               * We don't know what's going on. Turn off the
2128               * interrupt source and try to continue.
2129               */
2130              printk("aic7xxx_isr: sstat1 = 0x%x\n", status);
2131              outb(status, CLRSINT1(base));
2132              UNPAUSE_SEQUENCER(p);
2133              outb(CLRSCSIINT, CLRINT(base));
2134              scb = NULL;
2135           }
2136         }
2137       }
2138     }  /* else */
2139   }
2140 
2141   if (intstat & CMDCMPLT)
2142   {
2143     int complete;
2144 
2145     /*
2146      * The sequencer will continue running when it
2147      * issues this interrupt. There may be >1 commands
2148      * finished, so loop until we've processed them all.
2149      */
2150     do {
2151       complete = inb(QOUTFIFO(base));
2152 
2153       scb = &(p->scb_array[complete]);
2154       if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
2155       {
2156         printk("aic7xxx warning: "
2157                "no command for scb %d (cmdcmplt)\n"
2158                "QOUTCNT = %d, SCB state = 0x%x, CMD = 0x%x\n",
2159                complete, inb(QOUTFIFO(base)),
2160                scb->state, (unsigned int) scb->cmd);
2161         outb(CLRCMDINT, CLRINT(base));
2162         continue;
2163       }
2164       cmd = scb->cmd;
2165 
2166       cmd->result = (aic7xxx_error(cmd) << 16) | aic7xxx_status(cmd);
2167       if ((cmd->flags & WAS_SENSE) && !(cmd->flags & ASKED_FOR_SENSE))
2168       { /* Got sense information. */
2169         cmd->flags = cmd->flags & ASKED_FOR_SENSE;
2170       }
2171 #if 0
2172       printk("aic7xxx_intr: (complete) state = %d, cmd = 0x%x, free = 0x%x\n",
2173              scb->state, (unsigned int) scb->cmd, (unsigned int) p->free_scb);
2174 #endif
2175       /*
2176        * This is a critical section, since we don't want the
2177        * queue routine mucking with the host data.
2178        */
2179       save_flags(flags);
2180       cli();
2181 
2182       scb->state = SCB_FREE;
2183       scb->next = p->free_scb;
2184       scb->cmd = NULL;
2185       p->free_scb = &(p->scb_array[scb->position]);
2186 
2187       restore_flags(flags);
2188 #if 0
2189   if (scb != &p->scb_array[scb->position])
2190   {
2191     printk("aic7xxx_isr: (complete) address mismatch, pos %d\n", scb->position);
2192   }
2193   printk("aic7xxx_isr: (complete) state = %d, cmd = 0x%x, free = 0x%x\n",
2194          scb->state, (unsigned int) scb->cmd, (unsigned int) p->free_scb);
2195 #endif
2196 
2197       cmd->scsi_done(cmd);
2198 
2199       /*
2200        * Clear interrupt status before checking
2201        * the output queue again. This eliminates
2202        * a race condition whereby a command could
2203        * complete between the queue poll and the
2204        * interrupt clearing, so notification of the
2205        * command being complete never made it back
2206        * up to the kernel.
2207        */
2208       outb(CLRCMDINT, CLRINT(base));
2209     } while (inb(QOUTCNT(base)));
2210   }
2211 }
2212 
2213 /*+F*************************************************************************
2214  * Function:
2215  *   aic7xxx_probe
2216  *
2217  * Description:
2218  *   Probing for EISA boards: it looks like the first two bytes
2219  *   are a manufacturer code - three characters, five bits each:
2220  *
2221  *               BYTE 0   BYTE 1   BYTE 2   BYTE 3
2222  *              ?1111122 22233333 PPPPPPPP RRRRRRRR
2223  *
2224  *   The characters are baselined off ASCII '@', so add that value
2225  *   to each to get the real ASCII code for it. The next two bytes
2226  *   appear to be a product and revision number, probably vendor-
2227  *   specific. This is what is being searched for at each port,
2228  *   and what should probably correspond to the ID= field in the
2229  *   ECU's .cfg file for the card - if your card is not detected,
2230  *   make sure your signature is listed in the array.
2231  *
2232  *   The fourth byte's lowest bit seems to be an enabled/disabled
2233  *   flag (rest of the bits are reserved?).
2234  *-F*************************************************************************/
2235 static aha_type
2236 aic7xxx_probe(int slot, int base)
     /*  */
2237 {
2238   int i;
2239   unsigned char buf[4];
2240 
2241   static struct {
2242     int n;
2243     unsigned char signature[sizeof(buf)];
2244     aha_type type;
2245   } AIC7xxx[] = {
2246     { 4, { 0x04, 0x90, 0x77, 0x71 }, AIC_274x },  /* host adapter 274x */
2247     { 4, { 0x04, 0x90, 0x77, 0x70 }, AIC_274x },  /* motherboard 274x  */
2248     { 4, { 0x04, 0x90, 0x77, 0x56 }, AIC_284x },  /* 284x, BIOS enabled */
2249     { 4, { 0x04, 0x90, 0x77, 0x57 }, AIC_284x }   /* 284x, BIOS disabled */
2250   };
2251 
2252   /*
2253    * The VL-bus cards need to be primed by
2254    * writing before a signature check.
2255    */
2256   for (i = 0; i < sizeof(buf); i++)
2257   {
2258     outb(0x80 + i, base);
2259     buf[i] = inb(base + i);
2260   }
2261 
2262   for (i = 0; i < NUMBER(AIC7xxx); i++)
2263   {
2264     /*
2265      * Signature match on enabled card?
2266      */
2267     if (!memcmp(buf, AIC7xxx[i].signature, AIC7xxx[i].n))
2268     {
2269       if (inb(base + 4) & 1)
2270       {
2271         return(AIC7xxx[i].type);
2272       }
2273 
2274       printk("aic7xxx disabled at slot %d, ignored\n", slot);
2275     }
2276   }
2277 
2278   return(AIC_NONE);
2279 }
2280 
2281 /*+F*************************************************************************
2282  * Function:
2283  *   read_seeprom
2284  *
2285  * Description:
2286  *   Reads the serial EEPROM and returns 1 if successful and 0 if
2287  *   not successful.
2288  *
2289  *   The instruction set of the 93C46 chip is as follows:
2290  *
2291  *               Start  OP
2292  *     Function   Bit  Code  Address    Data     Description
2293  *     -------------------------------------------------------------------
2294  *     READ        1    10   A5 - A0             Reads data stored in memory,
2295  *                                               starting at specified address
2296  *     EWEN        1    00   11XXXX              Write enable must preceed
2297  *                                               all programming modes
2298  *     ERASE       1    11   A5 - A0             Erase register A5A4A3A2A1A0
2299  *     WRITE       1    01   A5 - A0   D15 - D0  Writes register
2300  *     ERAL        1    00   10XXXX              Erase all registers
2301  *     WRAL        1    00   01XXXX    D15 - D0  Writes to all registers
2302  *     EWDS        1    00   00XXXX              Disables all programming
2303  *                                               instructions
2304  *     *Note: A value of X for address is a don't care condition.
2305  *
2306  *   The 93C46 has a four wire interface: clock, chip select, data in, and
2307  *   data out.  In order to perform one of the above functions, you need
2308  *   to enable the chip select for a clock period (typically a minimum of
2309  *   1 usec, with the clock high and low a minimum of 750 and 250 nsec
2310  *   respectively.  While the chip select remains high, you can clock in
2311  *   the instructions (above) starting with the start bit, followed by the
2312  *   OP code, Address, and Data (if needed).  For the READ instruction, the
2313  *   requested 16-bit register contents is read from the data out line but
2314  *   is preceded by an initial zero (leading 0, followed by 16-bits, MSB
2315  *   first).  The clock cycling from low to high initiates the next data
2316  *   bit to be sent from the chip.
2317  *
2318  *   The 7870 interface to the 93C46 serial EEPROM is through the SEECTL
2319  *   register.  After successful arbitration for the memory port, the
2320  *   SEECS bit of the SEECTL register is connected to the chip select.
2321  *   The SEECK, SEEDO, and SEEDI are connected to the clock, data out,
2322  *   and data in lines respectively.  The SEERDY bit of SEECTL is useful
2323  *   in that it gives us an 800 nsec timer.  After a write to the SEECTL
2324  *   register, the SEERDY goes high 800 nsec later.  The one exception
2325  *   to this is when we first request access to the memory port.  The
2326  *   SEERDY goes high to signify that access has been granted and, for
2327  *   this case, has no implied timing.
2328  *
2329  *-F*************************************************************************/
2330 static int
2331 read_seeprom(int base, struct seeprom_config *sc)
     /*  */
2332 {
2333   int i = 0, k = 0;
2334   unsigned long timeout;
2335   unsigned char temp;
2336   unsigned short checksum = 0;
2337   unsigned short *seeprom = (unsigned short *) sc;
2338   struct seeprom_cmd {
2339     unsigned char len;
2340     unsigned char bits[3];
2341   };
2342   struct seeprom_cmd seeprom_read = {3, {1, 1, 0}};
2343 
2344 #define CLOCK_PULSE(p) \
2345   while ((inb(SEECTL(base)) & SEERDY) == 0)     \
2346   {                                             \
2347     ;  /* Do nothing */                         \
2348   }
2349 
2350   /*
2351    * Request access of the memory port.  When access is
2352    * granted, SEERDY will go high.  We use a 1 second
2353    * timeout which should be near 1 second more than
2354    * is needed.  Reason: after the 7870 chip reset, there
2355    * should be no contention.
2356    */
2357   outb(SEEMS, SEECTL(base));
2358   timeout = jiffies + 100;  /* 1 second timeout */
2359   while ((jiffies < timeout) && ((inb(SEECTL(base)) & SEERDY) == 0))
2360   {
2361     ;  /* Do nothing!  Wait for access to be granted. */
2362   }
2363   if ((inb(SEECTL(base)) & SEERDY) == 0)
2364   {
2365     outb (0, SEECTL(base));
2366     return (0);
2367   }
2368 
2369   /*
2370    * Read the first 32 registers of the seeprom.  For the 7870,
2371    * the 93C46 SEEPROM is a 1024-bit device with 64 16-bit registers
2372    * but only the first 32 are used by Adaptec BIOS.  The loop
2373    * will range from 0 to 31.
2374    */
2375   for (k = 0; k < (sizeof(*sc) / 2); k = k + 1)
2376   {
2377     /* Send chip select for one clock cycle. */
2378     outb(SEEMS | SEECK | SEECS, SEECTL(base));
2379     CLOCK_PULSE(base);
2380 
2381     /*
2382      * Now we're ready to send the read command followed by the
2383      * address of the 16-bit register we want to read.
2384      */
2385     for (i = 0; i < seeprom_read.len; i = i + 1)
2386     {
2387       temp = SEEMS | SEECS | (seeprom_read.bits[i] << 1);
2388       outb(temp, SEECTL(base));
2389       CLOCK_PULSE(base);
2390       temp = temp ^ SEECK;
2391       outb(temp, SEECTL(base));
2392       CLOCK_PULSE(base);
2393     }
2394     /* Send the 6 bit address (MSB first, LSB last). */
2395     for (i = 5; i >= 0; i = i - 1)
2396     {
2397       temp = k;
2398       temp = (temp >> i) & 1;  /* Mask out all but lower bit. */
2399       temp = SEEMS | SEECS | (temp << 1);
2400       outb(temp, SEECTL(base));
2401       CLOCK_PULSE(base);
2402       temp = temp ^ SEECK;
2403       outb(temp, SEECTL(base));
2404       CLOCK_PULSE(base);
2405     }
2406 
2407     /*
2408      * Now read the 16 bit register.  An initial 0 precedes the
2409      * register contents which begins with bit 15 (MSB) and ends
2410      * with bit 0 (LSB).  The initial 0 will be shifted off the
2411      * top of our word as we let the loop run from 0 to 16.
2412      */
2413     for (i = 0; i <= 16; i = i + 1)
2414     {
2415       temp = SEEMS | SEECS;
2416       outb(temp, SEECTL(base));
2417       CLOCK_PULSE(base);
2418       temp = temp ^ SEECK;
2419       seeprom[k] = (seeprom[k] << 1) | (inb(SEECTL(base)) & SEEDI);
2420       outb(temp, SEECTL(base));
2421       CLOCK_PULSE(base);
2422     }
2423 
2424     /*
2425      * The serial EEPROM has a checksum in the last word.  Keep a
2426      * running checksum for all words read except for the last
2427      * word.  We'll verify the checksum after all words have been
2428      * read.
2429      */
2430     if (k < (sizeof(*sc) / 2) - 1)
2431     {
2432       checksum = checksum + seeprom[k];
2433     }
2434 
2435     /* Reset the chip select for the next command cycle. */
2436     outb(SEEMS, SEECTL(base));
2437     CLOCK_PULSE(base);
2438     outb(SEEMS | SEECK, SEECTL(base));
2439     CLOCK_PULSE(base);
2440     outb(SEEMS, SEECTL(base));
2441     CLOCK_PULSE(base);
2442   }
2443 
2444   if (checksum != sc->checksum)
2445   {
2446     printk ("aic7xxx : SEEPROM checksum error, ignoring SEEPROM settings.\n");
2447     return (0);
2448   }
2449 
2450 #if 0
2451   printk ("Computed checksum 0x%x, checksum read 0x%x\n", checksum, sc->checksum);
2452   printk ("Serial EEPROM:");
2453   for (k = 0; k < (sizeof(*sc) / 2); k = k + 1)
2454   {
2455     if (((k % 8) == 0) && (k != 0))
2456     {
2457       printk ("\n              ");
2458     }
2459     printk (" 0x%x", seeprom[k]);
2460   }
2461   printk ("\n");
2462 #endif
2463 
2464   /* Release access to the memory port and the serial EEPROM. */
2465   outb(0, SEECTL(base));
2466   return (1);
2467 }
2468 
2469 /*+F*************************************************************************
2470  * Function:
2471  *   detect_maxscb
2472  *
2473  * Description:
2474  *   Return the maximum number of SCB's allowed for a given controller.
2475  *-F*************************************************************************/
2476 static int
2477 detect_maxscb(aha_type type, int base)
     /*  */
2478 {
2479   unsigned char sblkctl_reg;
2480   int maxscb = 0;
2481 
2482   switch (type)
2483   {
2484     case AIC_274x:
2485     case AIC_284x:
2486       /*
2487        * Check for Rev C or E boards. Rev E boards can supposedly have
2488        * more than 4 SCBs, while the Rev C boards are limited to 4 SCBs.
2489        * Until we know how to access more than 4 SCBs for the Rev E chips,
2490        * we limit them, along with the Rev C chips, to 4 SCBs.
2491        *
2492        * The Rev E boards have a read/write autoflush bit in the
2493        * SBLKCTL registor, while in the Rev C boards it is read only.
2494        */
2495       sblkctl_reg = inb(SBLKCTL(base)) ^ AUTOFLUSHDIS;
2496       outb(sblkctl_reg, SBLKCTL(base));
2497       if (inb(SBLKCTL(base)) == sblkctl_reg)
2498       {  /* We detected a Rev E board. */
2499         printk("aic7770: Rev E and subsequent; using 4 SCB's\n");
2500         outb(sblkctl_reg ^ AUTOFLUSHDIS, SBLKCTL(base));
2501         maxscb = 4;
2502       }
2503       else
2504       {
2505         printk("aic7770: Rev C and previous; using 4 SCB's\n");
2506         maxscb = 4;
2507       }
2508       break;
2509 
2510     case AIC_7850:
2511       maxscb = 3;
2512       break;
2513 
2514     case AIC_7870:
2515       maxscb = 16;
2516       break;
2517 
2518     case AIC_7872:
2519       /*
2520        * Really has 255, but we'll wait to verify that we access
2521        * them the same way and do not have to set the card to
2522        * use the memory port to access external SCB RAM.
2523        */
2524       maxscb = 16;
2525       break;
2526 
2527     case AIC_NONE:
2528       /*
2529        * This should never happen... But just in case.
2530        */
2531       break;
2532   }
2533 
2534   return(maxscb);
2535 }
2536 
2537 /*+F*************************************************************************
2538  * Function:
2539  *   aic7xxx_register
2540  *
2541  * Description:
2542  *   Register a Adaptec aic7xxx chip SCSI controller with the kernel.
2543  *-F*************************************************************************/
2544 static int
2545 aic7xxx_register(Scsi_Host_Template *template, aha_type type,
     /*  */
2546                  int base, unsigned char irq)
2547 {
2548   static char * board_name[] = {"", "274x", "284x", "7870", "7850", "7872"};
2549   int i;
2550   unsigned char sblkctl;
2551   int max_targets;
2552   int found = 1;
2553   unsigned char target_settings;
2554   unsigned char scsi_conf;
2555   int have_seeprom = 0;
2556   struct Scsi_Host *host;
2557   struct aic7xxx_host *p;
2558   struct aic7xxx_host_config config;
2559   struct seeprom_config sc;
2560 
2561   config.type = type;
2562   config.base = base;
2563   config.irq = irq;
2564   config.parity = AIC_UNKNOWN;
2565   config.low_term = AIC_UNKNOWN;
2566   config.high_term = AIC_UNKNOWN;
2567   config.busrtime = 0;
2568 
2569   /*
2570    * Lock out other contenders for our i/o space.
2571    */
2572   request_region(MINREG(base), MAXREG(base) - MINREG(base), "aic7xxx");
2573 
2574   switch (type)
2575   {
2576     case AIC_274x:
2577 #if 1
2578       printk("aha274x: aic7770 hcntrl=0x%x\n", inb(HCNTRL(config.base)));
2579 #endif
2580       /*
2581        * For some 274x boards, we must clear the CHIPRST bit
2582        * and pause the sequencer. For some reason, this makes
2583        * the driver work. For 284x boards, we give it a
2584        * CHIPRST just like the 294x boards.
2585        *
2586        * Use the BIOS settings to determine the interrupt
2587        * trigger type (level or edge) and use this value
2588        * for pausing and unpausing the sequencer.
2589        */
2590       config.unpause = (inb(HCNTRL(config.base)) & IRQMS) | INTEN;
2591       config.pause = config.unpause | PAUSE;
2592       config.extended = aic7xxx_extended;
2593 
2594       /*
2595        * I don't think we need to kick the reset again, the initial probe
2596        * does a reset, it seems that this is kicking a dead horse here.
2597        * So... I will try to just verify that the chip has come out of the
2598        * reset state and continue the same as the 284x.
2599        * In the Calgary version of the driver:
2600        *   1) Chip Reset
2601        *   2) Set unpause to IRQMS | INTEN
2602        *   3) If an interrupt occured without any commands queued, the
2603        *      unpause was set to just INTEN
2604        * I changed the initial reset code to just mask in the CHIPRST bit
2605        * and try to leave the other settings alone.
2606        *
2607        * I don't think we need the warning about chip reset not being clear.
2608        * On both my test machines (2842 & 2940), they work just fine with a
2609        * HCNTRL() of 0x5 (PAUSE | CHIPRST). Notice though, the 274x also
2610        * adds the INTEN flag, where neither the 284x or 294x do.
2611        */
2612       outb(config.pause | CHIPRST, HCNTRL(config.base));
2613       aic7xxx_delay(1);
2614       if (inb(HCNTRL(config.base)) & CHIPRST)
2615       {
2616         printk("aic7xxx_register: Chip reset not cleared; clearing manually.\n");
2617       }
2618       outb(config.pause, HCNTRL(config.base));
2619 
2620       /*
2621        * Just to be on the safe side with the 274x, we will re-read the irq
2622        * since there was some issue about reseting the board.
2623        */
2624       config.irq = inb(HA_INTDEF(config.base)) & 0x0F;
2625       config.busrtime = inb(HA_SCSICONF(config.base)) & 0x3C;
2626 
2627       /*
2628        * A reminder until this can be detected automatically.
2629        */
2630       printk("aha274x: extended translation %sabled\n",
2631              config.extended ? "en" : "dis");
2632       break;
2633 
2634     case AIC_284x:
2635 #if 1
2636       printk("aha284x: aic7770 hcntrl=0x%x\n", inb(HCNTRL(config.base)));
2637 #endif
2638       outb(CHIPRST, HCNTRL(config.base));
2639       config.unpause = UNPAUSE_284X;
2640       config.pause = REQ_PAUSE; /* DWG would like to be like the rest */
2641       config.extended = aic7xxx_extended;
2642       config.irq = inb(HA_INTDEF(config.base)) & 0x0F;
2643 
2644       /*
2645        * A reminder until this can be detected automatically.
2646        */
2647       printk("aha284x: extended translation %sabled\n",
2648              config.extended ? "en" : "dis");
2649       break;
2650 
2651     case AIC_7850:
2652     case AIC_7870:
2653     case AIC_7872:
2654 #if 1
2655       printk("aic%s hcntrl=0x%x\n", board_name[type], inb(HCNTRL(config.base)));
2656 #endif
2657 
2658       outb(CHIPRST, HCNTRL(config.base));
2659       config.unpause = UNPAUSE_294X;
2660       config.pause = config.unpause | PAUSE;
2661       config.extended = aic7xxx_extended;
2662       config.scsi_id = 7;
2663 
2664       printk ("aic78xx: Reading SEEPROM... ");
2665       have_seeprom = read_seeprom(base, &sc);
2666       if (! have_seeprom)
2667       {
2668         printk ("Unable to read SEEPROM\n");
2669       }
2670       else
2671       {
2672         printk ("done\n");
2673         config.extended = (sc.bios_control & CFEXTEND) >> 7;
2674         config.scsi_id = (sc.brtime_id & CFSCSIID);
2675         config.parity = (sc.adapter_control & CFSPARITY) ?
2676                          AIC_ENABLED : AIC_DISABLED;
2677         config.low_term = (sc.adapter_control & CFSTERM) ?
2678                               AIC_ENABLED : AIC_DISABLED;
2679         config.high_term = (sc.adapter_control & CFWSTERM) ?
2680                               AIC_ENABLED : AIC_DISABLED;
2681         config.busrtime = (sc.brtime_id & CFBRTIME) >> 8;
2682       }
2683 
2684       /*
2685        * XXX - force data fifo threshold to 100%. Why does this
2686        *       need to be done?
2687        */
2688       outb(inb(DSPCISTATUS(config.base)) | DFTHRESH, DSPCISTATUS(config.base));
2689       outb(config.scsi_id | DFTHRESH, HA_SCSICONF(config.base));
2690 
2691       /*
2692        * In case we are a wide card, place scsi ID in second conf byte.
2693        */
2694       outb(config.scsi_id, (HA_SCSICONF(config.base) + 1));
2695 
2696       /*
2697        * A reminder until this can be detected automatically.
2698        */
2699       printk("aic%s: extended translation %sabled\n", board_name[type],
2700              config.extended ? "en" : "dis");
2701       break;
2702 
2703     default:
2704       panic("aic7xxx_register: internal error\n");
2705   }
2706 
2707   config.maxscb = detect_maxscb(type, base);
2708 
2709   if ((config.type == AIC_274x) || (config.type == AIC_284x))
2710   {
2711     if (config.pause & IRQMS)
2712     {
2713       printk("aic7xxx: Using Level Sensitive Interrupts\n");
2714     }
2715     else
2716     {
2717       printk("aic7xxx: Using Edge Triggered Interrupts\n");
2718     }
2719   }
2720 
2721   /*
2722    * Read the bus type from the SBLKCTL register. Set the FLAGS
2723    * register in the sequencer for twin and wide bus cards.
2724    */
2725   sblkctl = inb(SBLKCTL(base)) & 0x0F;  /* mask out upper two bits */
2726   switch (sblkctl)
2727   {
2728     case 0:     /* narrow/normal bus */
2729       config.scsi_id = inb(HA_SCSICONF(base)) & 0x07;
2730       config.bus_type = AIC_SINGLE;
2731       outb(0, HA_FLAGS(base));
2732       break;
2733 
2734     case 2:     /* Wide bus */
2735       config.scsi_id = inb(HA_SCSICONF(base) + 1) & 0x0F;
2736       config.bus_type = AIC_WIDE;
2737       printk("aic7xxx : Enabling wide channel of %s-Wide\n",
2738              board_name[config.type]);
2739       outb(WIDE_BUS, HA_FLAGS(base));
2740       break;
2741 
2742     case 8:     /* Twin bus */
2743       config.scsi_id = inb(HA_SCSICONF(base)) & 0x07;
2744 #ifdef AIC7XXX_TWIN_SUPPORT
2745       config.scsi_id_b = inb(HA_SCSICONF(base) + 1) & 0x07;
2746       config.bus_type = AIC_TWIN;
2747       printk("aic7xxx : Enabled channel B of %s-Twin\n",
2748              board_name[config.type]);
2749       outb(TWIN_BUS, HA_FLAGS(base));
2750 #else
2751       config.bus_type = AIC_SINGLE;
2752       printk("aic7xxx : Channel B of %s-Twin will be ignored\n",
2753              board_name[config.type]);
2754       outb(0, HA_FLAGS(base));
2755 #endif
2756       break;
2757 
2758     default:
2759       printk("aic7xxx is an unsupported type 0x%x, please "
2760              "mail deang@ims.com\n", inb(SBLKCTL(base)));
2761       outb(0, HA_FLAGS(base));
2762       return(0);
2763   }
2764 
2765   /*
2766    * Clear the upper two bits. For the 294x cards, clearing the
2767    * upper two bits, will take the card out of diagnostic mode
2768    * and make the host adatper LED follow bus activity (will not
2769    * always be on).
2770    */
2771   outb(sblkctl, SBLKCTL(base));
2772 
2773   /*
2774    * The IRQ level in i/o port 4 maps directly onto the real
2775    * IRQ number. If it's ok, register it with the kernel.
2776    *
2777    * NB. the Adaptec documentation says the IRQ number is only
2778    *     in the lower four bits; the ECU information shows the
2779    *     high bit being used as well. Which is correct?
2780    *
2781    * The 294x cards (PCI) get their interrupt from PCI BIOS.
2782    */
2783   if (((config.type == AIC_274x) || (config.type == AIC_284x))
2784       && (config.irq < 9 || config.irq > 15))
2785   {
2786     printk("aic7xxx uses unsupported IRQ level, ignoring\n");
2787     return(0);
2788   }
2789 
2790   /*
2791    * Check the IRQ to see if it is shared by another aic7xxx
2792    * controller. If it is and sharing of IRQs is not defined,
2793    * then return 0 hosts found. If sharing of IRQs is allowed
2794    * or the IRQ is not shared by another host adapter, then
2795    * proceed.
2796    */
2797 #ifndef AIC7XXX_SHARE_IRQS
2798    if (aic7xxx_boards[config.irq] != NULL)
2799    {
2800      printk("aic7xxx_register: Sharing of IRQs is not configured.\n");
2801      return(0);
2802    }
2803 #endif
2804 
2805   /*
2806    * Print out debugging information before re-enabling
2807    * the card - a lot of registers on it can't be read
2808    * when the sequencer is active.
2809    */
2810   debug_config(&config);
2811 
2812   /*
2813    * Before registry, make sure that the offsets of the
2814    * struct scatterlist are what the sequencer will expect,
2815    * otherwise disable scatter-gather altogether until someone
2816    * can fix it. This is important since the sequencer will
2817    * DMA elements of the SG array in while executing commands.
2818    */
2819   if (template->sg_tablesize != SG_NONE)
2820   {
2821     struct scatterlist sg;
2822 
2823     if (SG_STRUCT_CHECK(sg))
2824     {
2825       printk("aic7xxx warning: kernel scatter-gather "
2826              "structures changed, disabling it\n");
2827       template->sg_tablesize = SG_NONE;
2828     }
2829   }
2830 
2831   /*
2832    * Register each "host" and fill in the returned Scsi_Host
2833    * structure as best we can. Some of the parameters aren't
2834    * really relevant for bus types beyond ISA, and none of the
2835    * high-level SCSI code looks at it anyway. Why are the fields
2836    * there? Also save the pointer so that we can find the
2837    * information when an IRQ is triggered.
2838    */
2839   host = scsi_register(template, sizeof(struct aic7xxx_host));
2840   host->can_queue = config.maxscb;
2841 #ifdef AIC7XXX_TAGGED_QUEUEING
2842   host->cmd_per_lun = 2;
2843 #else
2844   host->cmd_per_lun = 1;
2845 #endif
2846   host->this_id = config.scsi_id;
2847   host->irq = config.irq;
2848   if (config.bus_type == AIC_WIDE)
2849   {
2850     host->max_id = 16;
2851   }
2852   if (config.bus_type == AIC_TWIN)
2853   {
2854     host->max_channel = 1;
2855   }
2856 
2857   p = (struct aic7xxx_host *) host->hostdata;
2858 
2859   /* Initialize the scb array by setting the state to free. */
2860   for (i = 0; i < AIC7XXX_MAXSCB; i = i + 1)
2861   {
2862     p->scb_array[i].state = SCB_FREE;
2863     p->scb_array[i].next = NULL;
2864     p->scb_array[i].cmd = NULL;
2865   }
2866 
2867   p->isr_count = 0;
2868   p->a_scanned = 0;
2869   p->b_scanned = 0;
2870   p->base = config.base;
2871   p->maxscb = config.maxscb;
2872   p->numscb = 0;
2873   p->extended = config.extended;
2874   p->type = config.type;
2875   p->bus_type = config.bus_type;
2876   p->have_seeprom = have_seeprom;
2877   p->seeprom = sc;
2878   p->free_scb = NULL;
2879   p->next = NULL;
2880 
2881   p->unpause = config.unpause;
2882   p->pause = config.pause;
2883 
2884   if (aic7xxx_boards[config.irq] == NULL)
2885   {
2886     /*
2887      * Register IRQ with the kernel.
2888      */
2889     if (request_irq(config.irq, aic7xxx_isr, SA_INTERRUPT, "aic7xxx"))
2890     {
2891       printk("aic7xxx couldn't register irq %d, ignoring\n", config.irq);
2892       return(0);
2893     }
2894     aic7xxx_boards[config.irq] = host;
2895   }
2896   else
2897   {
2898     /*
2899      * We have found a host adapter sharing an IRQ of a previously
2900      * registered host adapter. Add this host adapter's Scsi_Host
2901      * to the beginning of the linked list of hosts at the same IRQ.
2902      */
2903     p->next = aic7xxx_boards[config.irq];
2904     aic7xxx_boards[config.irq] = host;
2905   }
2906 
2907   /*
2908    * Load the sequencer program, then re-enable the board -
2909    * resetting the AIC-7770 disables it, leaving the lights
2910    * on with nobody home. On the PCI bus you *may* be home,
2911    * but then your mailing address is dynamically assigned
2912    * so no one can find you anyway :-)
2913    */
2914   printk("aic7xxx: Downloading sequencer code..");
2915   aic7xxx_loadseq(base);
2916 
2917   /* Set Fast Mode and Enable the board */
2918   outb(FASTMODE, SEQCTL(base));
2919 
2920   if ((p->type == AIC_274x || p->type == AIC_284x))
2921   {
2922     outb(ENABLE, BCTL(base));
2923   }
2924 
2925   printk("done.\n");
2926 
2927   /*
2928    * Set the SCSI Id, SXFRCTL1, and SIMODE1, for both channels
2929    */
2930   if (p->bus_type == AIC_TWIN)
2931   {
2932     /*
2933      * The device is gated to channel B after a chip reset,
2934      * so set those values first.
2935      */
2936     outb(config.scsi_id_b, SCSIID(base));
2937     scsi_conf = inb(HA_SCSICONF(base) + 1) & (ENSPCHK | STIMESEL);
2938     scsi_conf = scsi_conf | ENSTIMER | ACTNEGEN | STPWEN;
2939     outb(scsi_conf, SXFRCTL1(base));
2940     outb(ENSELTIMO | ENSCSIPERR, SIMODE1(base));
2941     /* Select Channel A */
2942     outb(0, SBLKCTL(base));
2943   }
2944   outb(config.scsi_id, SCSIID(base));
2945   scsi_conf = inb(HA_SCSICONF(base)) & (ENSPCHK | STIMESEL);
2946   outb(scsi_conf | ENSTIMER | ACTNEGEN | STPWEN, SXFRCTL1(base));
2947   outb(ENSELTIMO | ENSCSIPERR, SIMODE1(base));
2948 
2949   /* Look at the information that board initialization or the board
2950    * BIOS has left us. In the lower four bits of each target's
2951    * scratch space any value other than 0 indicates that we should
2952    * initiate synchronous transfers. If it's zero, the user or the
2953    * BIOS has decided to disable synchronous negotiation to that
2954    * target so we don't activate the needsdtr flag.
2955    */
2956   p->needsdtr_copy = 0;
2957   p->sdtr_pending = 0;
2958   p->needwdtr_copy = 0;
2959   p->wdtr_pending = 0;
2960   if (p->bus_type == AIC_SINGLE)
2961   {
2962     max_targets = 8;
2963   }
2964   else
2965   {
2966     max_targets = 16;
2967   }
2968 
2969   for (i = 0; i < max_targets; i = i + 1)
2970   {
2971     if (have_seeprom)
2972     {
2973       target_settings = (sc.device_flags[i] & CFXFER) << 4;
2974       if (sc.device_flags[i] & CFSYNCH)
2975       {
2976         p->needsdtr_copy = p->needsdtr_copy | (0x01 << i);
2977       }
2978       if ((sc.device_flags[i] & CFWIDEB) && (p->bus_type == AIC_WIDE))
2979       {
2980         p->needwdtr_copy = p->needwdtr_copy | (0x01 << i);
2981       }
2982     }
2983     else
2984     {
2985       target_settings = inb(HA_TARG_SCRATCH(base) + i);
2986       if (target_settings & 0x0F)
2987       {
2988         p->needsdtr_copy = p->needsdtr_copy | (0x01 << i);
2989         /*
2990          * Default to asynchronous transfers (0 offset)
2991          */
2992         target_settings = target_settings & 0xF0;
2993       }
2994       /*
2995        * If we are not wide, forget WDTR. This makes the driver
2996        * work on some cards that don't leave these fields cleared
2997        * when BIOS is not installed.
2998        */
2999       if ((target_settings & 0x80) && (p->bus_type == AIC_WIDE))
3000       {
3001         p->needwdtr_copy = p->needwdtr_copy | (0x01 << i);
3002         target_settings = target_settings & 0x7F;
3003       }
3004     }
3005     outb(target_settings, (HA_TARG_SCRATCH(base) + i));
3006   }
3007 
3008   p->needsdtr = p->needsdtr_copy;
3009   p->needwdtr = p->needwdtr_copy;
3010   printk("NeedSdtr = 0x%x, 0x%x\n", p->needsdtr_copy, p->needsdtr);
3011   printk("NeedWdtr = 0x%x, 0x%x\n", p->needwdtr_copy, p->needwdtr);
3012 
3013   /* 
3014    * Clear the control byte for every SCB so that the sequencer
3015    * doesn't get confused and think that one of them is valid
3016    */
3017   for (i = 0; i < config.maxscb; i = i + 1)
3018   {
3019     outb(i, SCBPTR(base));
3020     outb(0, SCBARRAY(base));
3021   }
3022 
3023   /*
3024    * For reconnecting targets, the sequencer code needs to
3025    * know how many SCBs it has to search through.
3026    */
3027   outb(config.maxscb, HA_SCBCOUNT(base));
3028 
3029   /*
3030    * Clear the active flags - no targets are busy.
3031    */
3032   outb(0, HA_ACTIVE0(base));
3033   outb(0, HA_ACTIVE1(base));
3034 
3035   /* We don't have any waiting selections */
3036   outb (SCB_LIST_NULL, WAITING_SCBH(base));
3037   outb (SCB_LIST_NULL, WAITING_SCBT(base));
3038 
3039   /*
3040    * Reset the SCSI bus. Is this necessary?
3041    *   There may be problems for a warm boot without resetting
3042    *   the SCSI bus. Either BIOS settings in scratch RAM
3043    *   will not get reinitialized, or devices may stay at
3044    *   previous negotiated settings (SDTR and WDTR) while
3045    *   the driver will think that no negotiations have been
3046    *   performed.
3047    *
3048    * Some devices need a long time to "settle" after a SCSI
3049    * bus reset.
3050    */
3051 
3052   if (!aic7xxx_no_reset)
3053   {
3054     printk("Resetting the SCSI bus...\n");
3055     outb(SCSIRSTO, SCSISEQ(base));
3056     udelay(1000);
3057     outb(0, SCSISEQ(base));
3058     aic7xxx_delay(AIC7XXX_RESET_DELAY);
3059   }
3060 
3061   /*
3062    * Unpause the sequencer before returning and enable
3063    * interrupts - we shouldn't get any until the first
3064    * command is sent to us by the high-level SCSI code.
3065    */
3066   UNPAUSE_SEQUENCER(p);
3067   return(found);
3068 }
3069 
3070 /*+F*************************************************************************
3071  * Function:
3072  *   aic7xxx_detect
3073  *
3074  * Description:
3075  *   Try to detect and register an Adaptec 7770 or 7870 SCSI controller.
3076  *-F*************************************************************************/
3077 int
3078 aic7xxx_detect(Scsi_Host_Template *template)
     /*  */
3079 {
3080   aha_type type = AIC_NONE;
3081   int found = 0, slot, base;
3082   unsigned char irq = 0;
3083   int i;
3084 
3085   /*
3086    * Since we may allow sharing of IRQs, it is imperative
3087    * that we "null-out" the aic7xxx_boards array. It is
3088    * not guaranteed to be initialized to 0 (NULL). We use
3089    * a NULL entry to indicate that no prior hosts have
3090    * been found/registered for that IRQ.
3091    */
3092   for (i = 0; i <= MAXIRQ; i++)
3093   {
3094     aic7xxx_boards[i] = NULL;
3095   }
3096 
3097   /*
3098    * EISA/VL-bus card signature probe.
3099    */
3100   for (slot = MINSLOT; slot <= MAXSLOT; slot++)
3101   {
3102     base = SLOTBASE(slot);
3103 
3104     if (check_region(MINREG(base), MAXREG(base) - MINREG(base)))
3105     {
3106       /*
3107        * Some other driver has staked a
3108        * claim to this i/o region already.
3109        */
3110       continue;
3111     }
3112 
3113     type = aic7xxx_probe(slot, HID0(base));
3114     if (type != AIC_NONE)
3115     {
3116       printk("aic7xxx: hcntrl=0x%x\n", inb(HCNTRL(base)));
3117 #if 0
3118       outb(inb(HCNTRL(base)) | CHIPRST, HCNTRL(base));
3119       irq = inb(HA_INTDEF(base)) & 0x0F;
3120 #endif
3121 
3122       /*
3123        * We "find" a AIC-7770 if we locate the card
3124        * signature and we can set it up and register
3125        * it with the kernel without incident.
3126        */
3127       found += aic7xxx_register(template, type, base, irq);
3128     }
3129   }
3130 
3131 #ifdef CONFIG_PCI
3132 
3133 #define DEVREVID  0x08
3134 #define DEVCONFIG 0x40
3135 #define DEVSTATUS 0x41
3136 #define RAMPSM    0x02
3137 
3138 /* This should be defined in pci.h */
3139 #define PCI_DEVICE_ID_ADAPTEC_7850      0x5078
3140 #define PCI_DEVICE_ID_ADAPTEC_7872      0x7278
3141 
3142   /*
3143    * PCI-bus probe.
3144    */
3145   if (pcibios_present())
3146   {
3147     int error;
3148     int done = 0;
3149     unsigned int io_port;
3150     unsigned short index = 0;
3151     unsigned char pci_bus, pci_device_fn;
3152     unsigned char devrevid, devconfig, devstatus;
3153     char rev_id[] = {'B', 'C', 'D'};
3154 
3155     while (!done)
3156     {
3157       if ((!pcibios_find_device(PCI_VENDOR_ID_ADAPTEC,
3158                                 PCI_DEVICE_ID_ADAPTEC_294x,
3159                                 index, &pci_bus, &pci_device_fn)) ||
3160            (!pcibios_find_device(PCI_VENDOR_ID_ADAPTEC,
3161                                 PCI_DEVICE_ID_ADAPTEC_2940,
3162                                 index, &pci_bus, &pci_device_fn)))
3163       {
3164         type = AIC_7870;
3165       }
3166       else
3167       {
3168         if (!pcibios_find_device(PCI_VENDOR_ID_ADAPTEC,
3169                                 PCI_DEVICE_ID_ADAPTEC_7850,
3170                                 index, &pci_bus, &pci_device_fn))
3171         {
3172           type = AIC_7850;
3173         }
3174         else
3175         {
3176           if (!pcibios_find_device(PCI_VENDOR_ID_ADAPTEC,
3177                                   PCI_DEVICE_ID_ADAPTEC_7872,
3178                                   index, &pci_bus, &pci_device_fn))
3179           {
3180             type = AIC_7872;
3181           }
3182           else
3183           {
3184             type = AIC_NONE;
3185             done = 1;
3186           }
3187         }
3188       }
3189 
3190       if (!done)
3191       {
3192         /*
3193          * Read esundry information from PCI BIOS.
3194          */
3195         error = pcibios_read_config_dword(pci_bus, pci_device_fn,
3196                                           PCI_BASE_ADDRESS_0, &io_port);
3197 
3198         if (error)
3199         {
3200           panic("aic7xxx_detect: error 0x%x reading i/o port.\n", error);
3201         }
3202 
3203         error = pcibios_read_config_byte(pci_bus, pci_device_fn,
3204                                          PCI_INTERRUPT_LINE, &irq);
3205         if (error)
3206         {
3207           panic("aic7xxx_detect: error %d reading irq.\n", error);
3208         }
3209 
3210         /*
3211          * Make the base I/O register look like EISA and VL-bus.
3212          */
3213         base = io_port - 0xC01;
3214 
3215         printk("aic7xxx: hcntrl=0x%x\n", inb(HCNTRL(base)));
3216         outb(inb(HCNTRL(base)) | CHIPRST, HCNTRL(base));
3217 
3218         error = pcibios_read_config_byte(pci_bus, pci_device_fn,
3219                                          DEVREVID, &devrevid);
3220         if (devrevid < 3)
3221         {
3222           printk ("aic7xxx_detect: AIC-7870 Rev %c\n", rev_id[devrevid]);
3223         }
3224         error = pcibios_read_config_byte(pci_bus, pci_device_fn,
3225                                          DEVCONFIG, &devconfig);
3226         error = pcibios_read_config_byte(pci_bus, pci_device_fn,
3227                                          DEVSTATUS, &devstatus);
3228         printk ("aic7xxx_detect: devconfig 0x%x, devstatus 0x%x\n",
3229                 devconfig, devstatus);
3230         if (devstatus & RAMPSM)
3231         {
3232           printk ("aic7xxx_detect: detected external SCB RAM, "
3233                   "mail deang@ims.com for test patch");
3234         }
3235 
3236         found += aic7xxx_register(template, type, base, irq);
3237         index += 1;
3238       }
3239     }
3240   }
3241 #endif CONFIG_PCI
3242 
3243   template->name = (char *) aic7xxx_info(NULL);
3244   return(found);
3245 }
3246 
3247 
3248 /*+F*************************************************************************
3249  * Function:
3250  *   aic7xxx_buildscb
3251  *
3252  * Description:
3253  *   Build a SCB.
3254  *-F*************************************************************************/
3255 static void
3256 aic7xxx_buildscb(struct aic7xxx_host *p,
     /*  */
3257                  Scsi_Cmnd *cmd,
3258                  struct aic7xxx_scb *scb)
3259 {
3260   void *addr;
3261   unsigned length;
3262   unsigned short mask;
3263 
3264   /*
3265    * Setup the control byte if we need negotiation and have not
3266    * already requested it.
3267    */
3268 #ifdef AIC7XXX_TAGGED_QUEUEING
3269   if (cmd->device->tagged_supported)
3270   {
3271     if (cmd->device->tagged_queue == 0)
3272     {
3273       printk ("aic7xxx_buildscb: Enabling tagged queuing for target %d, "
3274               "channel %d\n", cmd->target, cmd->channel);
3275       cmd->device->tagged_queue = 1;
3276       cmd->device->current_tag = 1;  /* enable tagging */
3277     }
3278     cmd->tag = cmd->device->current_tag;
3279     cmd->device->current_tag = cmd->device->current_tag + 1;
3280     scb->control = scb->control | SCB_TE;
3281   }
3282 #endif
3283   mask = (0x01 << cmd->target);
3284   if ((p->needwdtr & mask) && !(p->wdtr_pending & mask))
3285   {
3286     p->wdtr_pending = p->wdtr_pending | mask;
3287     scb->control = scb->control | SCB_NEEDWDTR;
3288 #if 0
3289     printk("Sending WDTR request to target %d.\n", cmd->target);
3290 #endif
3291   }
3292   else
3293   {
3294     if ((p->needsdtr & mask) && !(p->sdtr_pending & mask))
3295     {
3296       p->sdtr_pending = p->sdtr_pending | mask;
3297       scb->control = scb->control | SCB_NEEDSDTR;
3298 #if 0
3299       printk("Sending SDTR request to target %d.\n", cmd->target);
3300 #endif
3301     }
3302   }
3303 
3304 #if 0
3305   printk("aic7xxx_queue: target %d, cmd 0x%x (size %u), wdtr 0x%x, mask 0x%x\n",
3306          cmd->target, cmd->cmnd[0], cmd->cmd_len, p->needwdtr, mask);
3307 #endif
3308   scb->target_channel_lun = ((cmd->target << 4) & 0xF0) |
3309         ((cmd->channel & 0x01) << 3) | (cmd->lun & 0x07);
3310 
3311   /*
3312    * The interpretation of request_buffer and request_bufflen
3313    * changes depending on whether or not use_sg is zero; a
3314    * non-zero use_sg indicates the number of elements in the
3315    * scatter-gather array.
3316    *
3317    * The AIC-7770 can't support transfers of any sort larger
3318    * than 2^24 (three-byte count) without backflips. For what
3319    * the kernel is doing, this shouldn't occur. I hope.
3320    */
3321   length = aic7xxx_length(cmd, 0);
3322 
3323   if (length > 0xFFFFFF)
3324   {
3325     panic("aic7xxx_buildscb: can't transfer > 2^24 - 1 bytes\n");
3326   }
3327 
3328   /*
3329    * XXX - this relies on the host data being stored in a
3330    *       little-endian format.
3331    */
3332   addr = cmd->cmnd;
3333   scb->SCSI_cmd_length = cmd->cmd_len;
3334   memcpy(scb->SCSI_cmd_pointer, &addr, sizeof(scb->SCSI_cmd_pointer));
3335 
3336   if (cmd->use_sg)
3337   {
3338 #if 0
3339     debug("aic7xxx_buildscb: SG used, %d segments, length %u\n",
3340           cmd->use_sg, length);
3341 #endif
3342     scb->SG_segment_count = cmd->use_sg;
3343     memcpy(scb->SG_list_pointer, &cmd->request_buffer,
3344            sizeof(scb->SG_list_pointer));
3345   }
3346   else
3347   {
3348 #if 0
3349     debug ("aic7xxx_buildscb: Creating scatterlist, addr=0x%lx, length=%d.\n",
3350            (unsigned long) cmd->request_buffer, cmd->request_bufflen);
3351 #endif
3352 #ifdef AIC7XXX_USE_SG
3353     scb->SG_segment_count = 1;
3354     scb->sg.address = (char *) cmd->request_buffer;
3355     scb->sg.length = cmd->request_bufflen;
3356     addr = &scb->sg;
3357     memcpy(scb->SG_list_pointer, &addr, sizeof(scb->SG_list_pointer));
3358 #else
3359     scb->SG_segment_count = 0;
3360     memcpy(scb->data_pointer, &cmd->request_buffer, sizeof(scb->data_pointer));
3361     memcpy(scb->data_count, &cmd->request_bufflen, 3);
3362 #endif
3363   }
3364 }
3365 
3366 /*+F*************************************************************************
3367  * Function:
3368  *   aic7xxx_queue
3369  *
3370  * Description:
3371  *   Queue a SCB to the controller.
3372  *-F*************************************************************************/
3373 int
3374 aic7xxx_queue(Scsi_Cmnd *cmd, void (*fn)(Scsi_Cmnd *))
     /*  */
3375 {
3376   long flags;
3377 #ifndef AIC7XXX_USE_DMA
3378   int old_scbptr;
3379 #endif
3380   struct aic7xxx_host *p;
3381   struct aic7xxx_scb *scb;
3382   unsigned char curscb;
3383 
3384   p = (struct aic7xxx_host *) cmd->host->hostdata;
3385 
3386   /* Check to see if channel was scanned. */
3387  if (!p->a_scanned && (cmd->channel == 0))
3388   {
3389     printk("aic7xxx: Scanning channel A for devices.\n");
3390     p->a_scanned = 1;
3391   }
3392   else
3393   {
3394     if (!p->b_scanned && (cmd->channel == 1))
3395     {
3396       printk("aic7xxx: Scanning channel B for devices.\n");
3397       p->b_scanned = 1;
3398     }
3399   }
3400 
3401 #if 0
3402   debug("aic7xxx_queue: cmd 0x%x (size %u), target %d, channel %d, lun %d\n",
3403         cmd->cmnd[0], cmd->cmd_len, cmd->target, cmd->channel,
3404         cmd->lun & 0x07);
3405 #endif
3406 
3407   /*
3408    * This is a critical section, since we don't want the
3409    * interrupt routine mucking with the host data or the
3410    * card. Since the kernel documentation is vague on
3411    * whether or not we are in a cli/sti pair already, save
3412    * the flags to be on the safe side.
3413    */
3414   save_flags(flags);
3415   cli();
3416 
3417   /*
3418    * Find a free slot in the SCB array to load this command
3419    * into. Since can_queue is set to the maximum number of
3420    * SCBs for the card, we should always find one.
3421    *
3422    * First try to find an scb in the free list. If there are
3423    * none in the free list, then check the current number of
3424    * of scbs and take an unused one from the scb array.
3425    */
3426   scb = p->free_scb;
3427   if (scb != NULL)
3428   { /* found one in the free list */
3429     p->free_scb = scb->next;   /* remove and update head of list */
3430     /*
3431      * Warning! For some unknown reason, the scb at the head
3432      * of the free list is not the same address that it should
3433      * be. That's why we set the scb pointer taken by the
3434      * position in the array. The scb at the head of the list
3435      * should match this address, but it doesn't.
3436      */
3437     scb = &(p->scb_array[scb->position]);
3438     scb->control = 0;
3439     scb->state = SCB_ACTIVE;
3440   }
3441   else
3442   {
3443     if (p->numscb >= p->maxscb)
3444     {
3445       panic("aic7xxx_queue: couldn't find a free scb\n");
3446     }
3447     else
3448     {
3449       /*
3450        * Initialize the scb within the scb array. The
3451        * position within the array is the position on
3452        * the board that it will be loaded.
3453        */
3454       scb = &(p->scb_array[p->numscb]);
3455       memset(scb, 0, sizeof(*scb));
3456 
3457       scb->position = p->numscb;
3458       p->numscb = p->numscb + 1;
3459       scb->state = SCB_ACTIVE;
3460       scb->next_waiting = SCB_LIST_NULL;
3461       memcpy(scb->host_scb, &scb, sizeof(scb));
3462 #ifdef AIC7XXX_USE_DMA
3463       scb->control = SCB_NEEDDMA;
3464 #endif
3465       PAUSE_SEQUENCER(p);
3466       curscb = inb(SCBPTR(p->base));
3467       outb(scb->position, SCBPTR(p->base));
3468       aic7xxx_putdmascb(p->base, scb);
3469       outb(curscb, SCBPTR(p->base));
3470       UNPAUSE_SEQUENCER(p);
3471       scb->control = 0;
3472     }
3473   }
3474 
3475   scb->cmd = cmd;
3476   aic7xxx_position(cmd) = scb->position;
3477 
3478   /*
3479    * Construct the SCB beforehand, so the sequencer is
3480    * paused a minimal amount of time.
3481    */
3482   aic7xxx_buildscb(p, cmd, scb);
3483 
3484 #if 0
3485   if (scb != &p->scb_array[scb->position])
3486   {
3487     printk("aic7xxx_queue: address of scb by position does not match scb address\n");
3488   }
3489   printk("aic7xxx_queue: SCB pos=%d, cmdptr=0x%x, state=%d, freescb=0x%x\n",
3490          scb->position, (unsigned int) scb->cmd,
3491          scb->state, (unsigned int) p->free_scb);
3492 #endif
3493   /*
3494    * Pause the sequencer so we can play with its registers -
3495    * wait for it to acknowledge the pause.
3496    *
3497    * XXX - should the interrupts be left on while doing this?
3498    */
3499   PAUSE_SEQUENCER(p);
3500 
3501   /*
3502    * Save the SCB pointer and put our own pointer in - this
3503    * selects one of the four banks of SCB registers. Load
3504    * the SCB, then write its pointer into the queue in FIFO
3505    * and restore the saved SCB pointer.
3506    */
3507 #ifdef AIC7XXX_USE_DMA
3508   aic7xxx_putscb(p->base, scb);
3509 #else
3510   old_scbptr = inb(SCBPTR(p->base));
3511   outb(scb->position, SCBPTR(p->base));
3512 
3513   aic7xxx_putscb(p->base, scb);
3514 
3515   outb(scb->position, QINFIFO(p->base));
3516   outb(old_scbptr, SCBPTR(p->base));
3517 #endif
3518   /*
3519    * Make sure the Scsi_Cmnd pointer is saved, the struct it
3520    * points to is set up properly, and the parity error flag
3521    * is reset, then unpause the sequencer and watch the fun
3522    * begin.
3523    */
3524   cmd->scsi_done = fn;
3525   aic7xxx_error(cmd) = DID_OK;
3526   aic7xxx_status(cmd) = 0;
3527 
3528   cmd->result = 0;
3529   memset (&cmd->sense_buffer, 0, sizeof (cmd->sense_buffer));
3530 
3531   UNPAUSE_SEQUENCER(p);
3532   restore_flags(flags);
3533   return(0);
3534 }
3535 
3536 /* return values from aic7xxx_kill */
3537 typedef enum {
3538   k_ok,             /* scb found and message sent */
3539   k_busy,           /* message already present */
3540   k_absent,         /* couldn't locate scb */
3541   k_disconnect,     /* scb found, but disconnected */
3542 } k_state;
3543 
3544 /*+F*************************************************************************
3545  * Function:
3546  *   aic7xxx_kill
3547  *
3548  * Description:
3549  *   This must be called with interrupts disabled - it's going to
3550  *   be messing around with the host data, and an interrupt being
3551  *   fielded in the middle could get ugly.
3552  *
3553  *   Since so much of the abort and reset code is shared, this
3554  *   function performs more magic than it really should. If the
3555  *   command completes ok, then it will call scsi_done with the
3556  *   result code passed in. The unpause parameter controls whether
3557  *   or not the sequencer gets unpaused - the reset function, for
3558  *   instance, may want to do something more aggressive.
3559  *
3560  *   Note that the command is checked for in our SCB_array first
3561  *   before the sequencer is paused, so if k_absent is returned,
3562  *   then the sequencer is NOT paused.
3563  *-F*************************************************************************/
3564 static k_state
3565 aic7xxx_kill(Scsi_Cmnd *cmd, unsigned char message,
     /*  */
3566              unsigned int result, int unpause)
3567 {
3568   struct aic7xxx_host *p;
3569   struct aic7xxx_scb *scb;
3570   int i, active_scb, found, queued;
3571   unsigned char scbsave[AIC7XXX_MAXSCB];
3572   unsigned char flags;
3573   int scb_control;
3574   k_state status;
3575 
3576   p = (struct aic7xxx_host *) cmd->host->hostdata;
3577   scb = &p->scb_array[aic7xxx_position(cmd)];
3578 
3579 #if 0
3580   printk("aic7xxx_kill: In the kill function...\n");
3581 #endif
3582   PAUSE_SEQUENCER(p);
3583 
3584   /*
3585    * Case 1: In the QINFIFO
3586    *
3587    * This is the best case, really. Check to see if the
3588    * command is still in the sequencer's input queue. If
3589    * so, simply remove it. Reload the queue afterward.
3590    */
3591   queued = inb(QINCNT(p->base));
3592 
3593   for (i = found = 0; i < (queued - found); i++)
3594   {
3595     scbsave[i] = inb(QINFIFO(p->base));
3596 
3597     if (scbsave[i] == scb->position)
3598     {
3599       found = 1;
3600       i = i - 1;
3601     }
3602   }
3603 
3604   for (queued = 0; queued < i; queued++)
3605   {
3606     outb(scbsave[queued], QINFIFO(p->base));
3607   }
3608 
3609   if (found)
3610   {
3611     status = k_ok;
3612     goto complete;
3613   }
3614 
3615   active_scb = inb(SCBPTR(p->base));
3616   /*
3617    * Case 2: Not the active command
3618    *
3619    * Check the current SCB bank. If it's not the one belonging
3620    * to the command we want to kill, select the scb we want to
3621    * abort and turn off the disconnected bit. The driver will
3622    * then abort the command and notify us of the abort.
3623    */
3624   if (active_scb != scb->position)
3625   {
3626     outb(scb->position, SCBPTR(p->base));
3627     scb_control = inb(SCBARRAY(p->base));
3628     scb_control = scb_control & ~SCB_DIS;
3629     outb(scb_control, SCBARRAY(p->base));
3630     outb(active_scb, SCBPTR(p->base));
3631     status = k_disconnect;
3632     goto complete;
3633   }
3634 
3635   scb_control = inb(SCBARRAY(p->base));
3636   if (scb_control & SCB_DIS)
3637   {
3638     scb_control = scb_control & ~SCB_DIS;
3639     outb(scb_control, SCBARRAY(p->base));
3640     status = k_disconnect;
3641     goto complete;
3642   }
3643 
3644   /*
3645    * Presumably at this point our target command is active. Check
3646    * to see if there's a message already in effect. If not, place
3647    * our message in and assert ATN so the target goes into MESSAGE
3648    * OUT phase.
3649    */
3650   flags = inb(HA_FLAGS(p->base));
3651   if (flags & ACTIVE_MSG)
3652   {
3653     /*
3654      * If there is a message in progress, reset the bus
3655      * and have all devices renegotiate.
3656      */
3657     if (cmd->channel & 0x01)
3658     {
3659       p->needsdtr = p->needsdtr_copy & 0xFF00;
3660       p->sdtr_pending = p->sdtr_pending & 0x00FF;
3661       outb(0, HA_ACTIVE1(p->base));
3662     }
3663     else
3664     {
3665       if (p->bus_type == AIC_WIDE)
3666       {
3667         p->needsdtr = p->needsdtr_copy;
3668         p->needwdtr = p->needwdtr_copy;
3669         p->sdtr_pending = 0;
3670         p->wdtr_pending = 0;
3671         outb(0, HA_ACTIVE0(p->base));
3672         outb(0, HA_ACTIVE1(p->base));
3673       }
3674       else
3675       {
3676         p->needsdtr = p->needsdtr_copy & 0x00FF;
3677         p->sdtr_pending = p->sdtr_pending & 0xFF00;
3678         outb(0, HA_ACTIVE0(p->base));
3679       }
3680     }
3681     /* Reset the bus. */
3682     outb(SCSIRSTO, SCSISEQ(p->base));
3683     udelay(1000);
3684     outb(0, SCSISEQ(p->base));
3685     aic7xxx_delay(AIC7XXX_RESET_DELAY);
3686 
3687     status = k_busy;
3688     goto complete;
3689   }
3690 
3691   outb(flags | ACTIVE_MSG, HA_FLAGS(p->base));    /* active message */
3692   outb(1, HA_MSG_LEN(p->base));                   /* length = 1 */
3693   outb(message, HA_MSG_START(p->base));           /* message body */
3694 
3695   /*
3696    * Assert ATN. Use the value of SCSISIGO saved by the
3697    * sequencer code so we don't alter its contents radically
3698    * in the middle of something critical.
3699    */
3700   outb(inb(HA_SIGSTATE(p->base)) | 0x10, SCSISIGO(p->base));
3701 
3702   status = k_ok;
3703 
3704   /*
3705    * The command has been killed. Do the bookkeeping, unpause
3706    * the sequencer, and notify the higher-level SCSI code.
3707    */
3708 complete:
3709   if (unpause)
3710   {
3711     UNPAUSE_SEQUENCER(p);
3712   }
3713 
3714   /*
3715    * Mark the scb as free and clear the scbs command pointer.
3716    * Add the scb to the head of the free list being careful
3717    * to preserve the next pointers.
3718    */
3719   scb->state = SCB_FREE;          /* mark the scb as free */
3720   scb->cmd = NULL;                /* clear the command pointer */
3721   scb->next = p->free_scb;        /* preserve next pointer */
3722   p->free_scb = scb;              /* add at head of free list */
3723   cmd->result = cmd->result << 16;
3724   cmd->scsi_done(cmd);
3725   return(status);
3726 }
3727 
3728 /*+F*************************************************************************
3729  * Function:
3730  *   aic7xxx_abort
3731  *
3732  * Description:
3733  *   Abort the current SCSI command(s).
3734  *-F*************************************************************************/
3735 int
3736 aic7xxx_abort(Scsi_Cmnd *cmd)
     /*  */
3737 {
3738   int rv;
3739   long flags;
3740 
3741   save_flags(flags);
3742   cli();
3743 
3744   switch (aic7xxx_kill(cmd, ABORT, DID_ABORT, !0))
3745   {
3746     case k_ok:          rv = SCSI_ABORT_SUCCESS;        break;
3747     case k_busy:        rv = SCSI_ABORT_BUSY;           break;
3748     case k_absent:      rv = SCSI_ABORT_NOT_RUNNING;    break;
3749     case k_disconnect:  rv = SCSI_ABORT_SNOOZE;         break;
3750     default:            panic("aic7xxx_abort: internal error\n");
3751   }
3752 
3753   restore_flags(flags);
3754   return(rv);
3755 }
3756 
3757 /*+F*************************************************************************
3758  * Function:
3759  *   aic7xxx_reset
3760  *
3761  * Description:
3762  *   Resetting the bus always succeeds - is has to, otherwise the
3763  *   kernel will panic! Try a surgical technique - sending a BUS
3764  *   DEVICE RESET message - on the offending target before pulling
3765  *   the SCSI bus reset line.
3766  *-F*************************************************************************/
3767 int
3768 aic7xxx_reset(Scsi_Cmnd *cmd)
     /*  */
3769 {
3770   long flags;
3771   struct aic7xxx_host *p;
3772 
3773   p = (struct aic7xxx_host *) cmd->host->hostdata;
3774   save_flags(flags);
3775   cli();
3776 
3777   switch (aic7xxx_kill(cmd, BUS_DEVICE_RESET, DID_RESET, 0))
3778   {
3779     case k_ok:
3780       /*
3781        * The RESET message was sent to the target
3782        * with no problems. Flag that target as
3783        * needing a SDTR negotiation on the next
3784        * connection and restart the sequencer.
3785        */
3786       p->needsdtr = p->needsdtr & (1 << cmd->target);
3787       UNPAUSE_SEQUENCER(p);
3788       break;
3789 
3790     case k_absent:
3791       /*
3792        * The sequencer will not be paused if aic7xxx_kill()
3793        * couldn't find the command.
3794        */
3795       PAUSE_SEQUENCER(p);
3796       /* falls through */
3797 
3798     case k_busy:
3799       cmd->result = DID_RESET << 16;  /* return reset code */
3800       cmd->scsi_done(cmd);
3801       break;
3802 
3803     case k_disconnect:
3804       /*
3805        * Do a hard reset of the SCSI bus. According to the
3806        * SCSI-2 draft specification, reset has to be asserted
3807        * for at least 25us. I'm invoking the kernel delay
3808        * function for 30us since I'm not totally trusting of
3809        * the busy loop timing.
3810        *
3811        * XXX - I'm not convinced this works. I tried resetting
3812        *       the bus before, trying to get the devices on the
3813        *       bus to revert to asynchronous transfer, and it
3814        *       never seemed to work.
3815        */
3816       debug("aic7xxx: attempting to reset scsi bus and card\n");
3817 
3818       outb(SCSIRSTO, SCSISEQ(p->base));
3819       udelay(1000);
3820       outb(0, SCSISEQ(p->base));
3821       aic7xxx_delay(AIC7XXX_RESET_DELAY);
3822 
3823       UNPAUSE_SEQUENCER(p);
3824 
3825       /*
3826        * Locate the command and return a "reset" status
3827        * for it. This is not completely correct and will
3828        * probably return to haunt me later.
3829        */
3830       cmd->result = DID_RESET << 16;  /* return reset code */
3831       cmd->scsi_done(cmd);
3832       break;
3833 
3834     default:
3835       panic("aic7xxx_reset: internal error\n");
3836   }
3837 
3838   restore_flags(flags);
3839   return(SCSI_RESET_SUCCESS);
3840 }
3841 
3842 /*+F*************************************************************************
3843  * Function:
3844  *   aic7xxx_biosparam
3845  *
3846  * Description:
3847  *   Return the disk geometry for the given SCSI device.
3848  *-F*************************************************************************/
3849 int
3850 aic7xxx_biosparam(Disk *disk, int devno, int geom[])
     /*  */
3851 {
3852   int heads, sectors, cylinders;
3853   struct aic7xxx_host *p;
3854 
3855   p = (struct aic7xxx_host *) disk->device->host->hostdata;
3856 
3857   /*
3858    * XXX - if I could portably find the card's configuration
3859    *       information, then this could be autodetected instead
3860    *       of left to a boot-time switch.
3861    */
3862   heads = 64;
3863   sectors = 32;
3864   cylinders = disk->capacity / (heads * sectors);
3865 
3866   if (p->extended && cylinders > 1024)
3867   {
3868     heads = 255;
3869     sectors = 63;
3870     cylinders = disk->capacity / (255 * 63);
3871   }
3872 
3873   geom[0] = heads;
3874   geom[1] = sectors;
3875   geom[2] = cylinders;
3876 
3877   return(0);
3878 }
3879 
3880 #ifdef MODULE
3881 /* Eventually this will go into an include file, but this will be later */
3882 Scsi_Host_Template driver_template = AIC7XXX;
3883 
3884 #include "scsi_module.c"
3885 #endif
3886
/* */
root/drivers/scsi/aic7xxx.c

DEFINITIONS
