drivers/sound/ad1848.c

/* */
This source file includes following definitions.
ad_read
ad_write
wait_for_calibration
ad_mute
ad_unmute
ad_enter_MCE
ad_leave_MCE
ad1848_set_recmask
change_bits
ad1848_mixer_get
ad1848_mixer_set
ad1848_mixer_reset
ad1848_mixer_ioctl
ad1848_open
ad1848_close
set_speed
set_channels
set_format
ad1848_ioctl
ad1848_output_block
ad1848_start_input
ad1848_prepare_for_IO
ad1848_reset
ad1848_halt
ad1848_detect
ad1848_init
ad1848_interrupt
probe_ms_sound
attach_ms_sound
   1 /*
   2  * sound/ad1848.c
   3  *
   4  * The low level driver for the AD1848/CS4248 codec chip which
   5  * is used for example in the MS Sound System.
   6  *
   7  * The CS4231 which is used in the GUS MAX and some other cards is
   8  * upwards compatible with AD1848 and this driver is able to drive it.
   9  *
  10  * CS4231A and AD1845 are upward compatible with CS4231. However
  11  * the new features of these chips are different.
  12  *
  13  * CS4232 is a PnP audio chip which contains a CS4231A.
  14  *
  15  * Copyright by Hannu Savolainen 1994, 1995
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: 1. Redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer. 2.
  21  * Redistributions in binary form must reproduce the above copyright notice,
  22  * this list of conditions and the following disclaimer in the documentation
  23  * and/or other materials provided with the distribution.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY
  26  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  27  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  28  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
  29  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  30  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  31  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  32  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  33  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  34  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  35  * SUCH DAMAGE.
  36  *
  37  * Modified:
  38  *  Riccardo Facchetti  24 Mar 1995
  39  *  - Added the Audio Excel DSP 16 initialization routine.
  40  */
  41 
  42 #define DEB(x)
  43 #define DEB1(x)
  44 #include "sound_config.h"
  45 
  46 #if defined(CONFIGURE_SOUNDCARD) && !defined(EXCLUDE_AD1848)
  47 
  48 #include "ad1848_mixer.h"
  49 
  50 #define IMODE_NONE              0
  51 #define IMODE_OUTPUT            1
  52 #define IMODE_INPUT             2
  53 #define IMODE_INIT              3
  54 #define IMODE_MIDI              4
  55 
  56 typedef struct
  57   {
  58     int             base;
  59     int             irq;
  60     int             dma_capture, dma_playback;
  61     int             dual_dma;   /* 1, when two DMA channels allocated */
  62     unsigned char   MCE_bit;
  63     unsigned char   saved_regs[16];
  64 
  65     int             speed;
  66     unsigned char   speed_bits;
  67     int             channels;
  68     int             audio_format;
  69     unsigned char   format_bits;
  70 
  71     int             xfer_count;
  72     int             irq_mode;
  73     int             intr_active;
  74     int             opened;
  75     char           *chip_name;
  76     int             mode;
  77 
  78     /* Mixer parameters */
  79     int             recmask;
  80     int             supported_devices;
  81     int             supported_rec_devices;
  82     unsigned short  levels[32];
  83   }
  84 
  85 ad1848_info;
  86 
  87 static int      nr_ad1848_devs = 0;
  88 static char     irq2dev[16] =
  89 {-1, -1, -1, -1, -1, -1, -1, -1,
  90  -1, -1, -1, -1, -1, -1, -1, -1};
  91 
  92 static char     mixer2codec[MAX_MIXER_DEV] =
  93 {0};
  94 
  95 static int      ad_format_mask[3 /*devc->mode */ ] =
  96 {
  97   0,
  98   AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,
  99   AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_U16_LE | AFMT_IMA_ADPCM
 100 };
 101 
 102 static ad1848_info dev_info[MAX_AUDIO_DEV];
 103 
 104 #define io_Index_Addr(d)        ((d)->base)
 105 #define io_Indexed_Data(d)      ((d)->base+1)
 106 #define io_Status(d)            ((d)->base+2)
 107 #define io_Polled_IO(d)         ((d)->base+3)
 108 
 109 static int      ad1848_open (int dev, int mode);
 110 static void     ad1848_close (int dev);
 111 static int      ad1848_ioctl (int dev, unsigned int cmd, unsigned int arg, int local);
 112 static void     ad1848_output_block (int dev, unsigned long buf, int count, int intrflag, int dma_restart);
 113 static void     ad1848_start_input (int dev, unsigned long buf, int count, int intrflag, int dma_restart);
 114 static int      ad1848_prepare_for_IO (int dev, int bsize, int bcount);
 115 static void     ad1848_reset (int dev);
 116 static void     ad1848_halt (int dev);
 117 void            ad1848_interrupt (INT_HANDLER_PARMS (irq, dummy));
 118 
 119 static int
 120 ad_read (ad1848_info * devc, int reg)
     /*  */
 121 {
 122   unsigned long   flags;
 123   int             x;
 124   int             timeout = 900000;
 125 
 126   while (timeout > 0 && INB (devc->base) == 0x80)       /*Are we initializing */
 127     timeout--;
 128 
 129   DISABLE_INTR (flags);
 130   OUTB ((unsigned char) (reg & 0xff) | devc->MCE_bit, io_Index_Addr (devc));
 131   x = INB (io_Indexed_Data (devc));
 132   /*  printk("(%02x<-%02x) ", reg|devc->MCE_bit, x); */
 133   RESTORE_INTR (flags);
 134 
 135   return x;
 136 }
 137 
 138 static void
 139 ad_write (ad1848_info * devc, int reg, int data)
     /*  */
 140 {
 141   unsigned long   flags;
 142   int             timeout = 90000;
 143 
 144   while (timeout > 0 && INB (devc->base) == 0x80)       /*Are we initializing */
 145     timeout--;
 146 
 147   DISABLE_INTR (flags);
 148   OUTB ((unsigned char) (reg & 0xff) | devc->MCE_bit, io_Index_Addr (devc));
 149   OUTB ((unsigned char) (data & 0xff), io_Indexed_Data (devc));
 150   /* printk("(%02x->%02x) ", reg|devc->MCE_bit, data); */
 151   RESTORE_INTR (flags);
 152 }
 153 
 154 static void
 155 wait_for_calibration (ad1848_info * devc)
     /*  */
 156 {
 157   int             timeout = 0;
 158 
 159   /*
 160      * Wait until the auto calibration process has finished.
 161      *
 162      * 1)       Wait until the chip becomes ready (reads don't return 0x80).
 163      * 2)       Wait until the ACI bit of I11 gets on and then off.
 164    */
 165 
 166   timeout = 100000;
 167   while (timeout > 0 && INB (devc->base) & 0x80)
 168     timeout--;
 169   if (INB (devc->base) & 0x80)
 170     printk ("ad1848: Auto calibration timed out(1).\n");
 171 
 172   timeout = 100;
 173   while (timeout > 0 && !(ad_read (devc, 11) & 0x20))
 174     timeout--;
 175   if (!(ad_read (devc, 11) & 0x20))
 176     return;
 177 
 178   timeout = 20000;
 179   while (timeout > 0 && ad_read (devc, 11) & 0x20)
 180     timeout--;
 181   if (ad_read (devc, 11) & 0x20)
 182     printk ("ad1848: Auto calibration timed out(3).\n");
 183 }
 184 
 185 static void
 186 ad_mute (ad1848_info * devc)
     /*  */
 187 {
 188   int             i;
 189   unsigned char   prev;
 190 
 191   /*
 192      * Save old register settings and mute output channels
 193    */
 194   for (i = 6; i < 8; i++)
 195     {
 196       prev = devc->saved_regs[i] = ad_read (devc, i);
 197       ad_write (devc, i, prev | 0x80);
 198     }
 199 }
 200 
 201 static void
 202 ad_unmute (ad1848_info * devc)
     /*  */
 203 {
 204   int             i;
 205 
 206   /*
 207      * Restore back old volume registers (unmute)
 208    */
 209   for (i = 6; i < 8; i++)
 210     {
 211       ad_write (devc, i, devc->saved_regs[i] & ~0x80);
 212     }
 213 }
 214 
 215 static void
 216 ad_enter_MCE (ad1848_info * devc)
     /*  */
 217 {
 218   unsigned long   flags;
 219   int             timeout = 1000;
 220   unsigned short  prev;
 221 
 222   while (timeout > 0 && INB (devc->base) == 0x80)       /*Are we initializing */
 223     timeout--;
 224 
 225   DISABLE_INTR (flags);
 226 
 227   devc->MCE_bit = 0x40;
 228   prev = INB (io_Index_Addr (devc));
 229   if (prev & 0x40)
 230     {
 231       RESTORE_INTR (flags);
 232       return;
 233     }
 234 
 235   OUTB (devc->MCE_bit, io_Index_Addr (devc));
 236   RESTORE_INTR (flags);
 237 }
 238 
 239 static void
 240 ad_leave_MCE (ad1848_info * devc)
     /*  */
 241 {
 242   unsigned long   flags;
 243   unsigned char   prev;
 244   int             timeout = 1000;
 245 
 246   while (timeout > 0 && INB (devc->base) == 0x80)       /*Are we initializing */
 247     timeout--;
 248 
 249   DISABLE_INTR (flags);
 250 
 251   devc->MCE_bit = 0x00;
 252   prev = INB (io_Index_Addr (devc));
 253   OUTB (0x00, io_Index_Addr (devc));    /* Clear the MCE bit */
 254 
 255   if ((prev & 0x40) == 0)               /* Not in MCE mode */
 256     {
 257       RESTORE_INTR (flags);
 258       return;
 259     }
 260 
 261   OUTB (0x00, io_Index_Addr (devc));    /* Clear the MCE bit */
 262   wait_for_calibration (devc);
 263   RESTORE_INTR (flags);
 264 }
 265 
 266 
 267 static int
 268 ad1848_set_recmask (ad1848_info * devc, int mask)
     /*  */
 269 {
 270   unsigned char   recdev;
 271   int             i, n;
 272 
 273   mask &= devc->supported_rec_devices;
 274 
 275   n = 0;
 276   for (i = 0; i < 32; i++)      /* Count selected device bits */
 277     if (mask & (1 << i))
 278       n++;
 279 
 280   if (n == 0)
 281     mask = SOUND_MASK_MIC;
 282   else if (n != 1)              /* Too many devices selected */
 283     {
 284       mask &= ~devc->recmask;   /* Filter out active settings */
 285 
 286       n = 0;
 287       for (i = 0; i < 32; i++)  /* Count selected device bits */
 288         if (mask & (1 << i))
 289           n++;
 290 
 291       if (n != 1)
 292         mask = SOUND_MASK_MIC;
 293     }
 294 
 295   switch (mask)
 296     {
 297     case SOUND_MASK_MIC:
 298       recdev = 2;
 299       break;
 300 
 301     case SOUND_MASK_LINE:
 302     case SOUND_MASK_LINE3:
 303       recdev = 0;
 304       break;
 305 
 306     case SOUND_MASK_CD:
 307     case SOUND_MASK_LINE1:
 308       recdev = 1;
 309       break;
 310 
 311     default:
 312       mask = SOUND_MASK_MIC;
 313       recdev = 2;
 314     }
 315 
 316   recdev <<= 6;
 317   ad_write (devc, 0, (ad_read (devc, 0) & 0x3f) | recdev);
 318   ad_write (devc, 1, (ad_read (devc, 1) & 0x3f) | recdev);
 319 
 320   devc->recmask = mask;
 321   return mask;
 322 }
 323 
 324 static void
 325 change_bits (unsigned char *regval, int dev, int chn, int newval)
     /*  */
 326 {
 327   unsigned char   mask;
 328   int             shift;
 329 
 330   if (mix_devices[dev][chn].polarity == 1)      /* Reverse */
 331     newval = 100 - newval;
 332 
 333   mask = (1 << mix_devices[dev][chn].nbits) - 1;
 334   shift = mix_devices[dev][chn].bitpos;
 335   newval = (int) ((newval * mask) + 50) / 100;  /* Scale it */
 336 
 337   *regval &= ~(mask << shift);  /* Clear bits */
 338   *regval |= (newval & mask) << shift;  /* Set new value */
 339 }
 340 
 341 static int
 342 ad1848_mixer_get (ad1848_info * devc, int dev)
     /*  */
 343 {
 344   if (!((1 << dev) & devc->supported_devices))
 345     return RET_ERROR (EINVAL);
 346 
 347   return devc->levels[dev];
 348 }
 349 
 350 static int
 351 ad1848_mixer_set (ad1848_info * devc, int dev, int value)
     /*  */
 352 {
 353   int             left = value & 0x000000ff;
 354   int             right = (value & 0x0000ff00) >> 8;
 355 
 356   int             regoffs;
 357   unsigned char   val;
 358 
 359   if (left > 100)
 360     left = 100;
 361   if (right > 100)
 362     right = 100;
 363 
 364   if (dev > 31)
 365     return RET_ERROR (EINVAL);
 366 
 367   if (!(devc->supported_devices & (1 << dev)))
 368     return RET_ERROR (EINVAL);
 369 
 370   if (mix_devices[dev][LEFT_CHN].nbits == 0)
 371     return RET_ERROR (EINVAL);
 372 
 373   /*
 374      * Set the left channel
 375    */
 376 
 377   regoffs = mix_devices[dev][LEFT_CHN].regno;
 378   val = ad_read (devc, regoffs);
 379   change_bits (&val, dev, LEFT_CHN, left);
 380   devc->levels[dev] = left | (left << 8);
 381   ad_write (devc, regoffs, val);
 382   devc->saved_regs[regoffs] = val;
 383 
 384   /*
 385      * Set the left right
 386    */
 387 
 388   if (mix_devices[dev][RIGHT_CHN].nbits == 0)
 389     return left | (left << 8);  /* Was just a mono channel */
 390 
 391   regoffs = mix_devices[dev][RIGHT_CHN].regno;
 392   val = ad_read (devc, regoffs);
 393   change_bits (&val, dev, RIGHT_CHN, right);
 394   ad_write (devc, regoffs, val);
 395   devc->saved_regs[regoffs] = val;
 396 
 397   devc->levels[dev] = left | (right << 8);
 398   return left | (right << 8);
 399 }
 400 
 401 static void
 402 ad1848_mixer_reset (ad1848_info * devc)
     /*  */
 403 {
 404   int             i;
 405 
 406   devc->recmask = 0;
 407   if (devc->mode == 2)
 408     devc->supported_devices = MODE2_MIXER_DEVICES;
 409   else
 410     devc->supported_devices = MODE1_MIXER_DEVICES;
 411 
 412   devc->supported_rec_devices = MODE1_REC_DEVICES;
 413 
 414   for (i = 0; i < SOUND_MIXER_NRDEVICES; i++)
 415     ad1848_mixer_set (devc, i, devc->levels[i] = default_mixer_levels[i]);
 416   ad1848_set_recmask (devc, SOUND_MASK_MIC);
 417 }
 418 
 419 static int
 420 ad1848_mixer_ioctl (int dev, unsigned int cmd, unsigned int arg)
     /*  */
 421 {
 422   ad1848_info    *devc;
 423 
 424   int             codec_dev = mixer2codec[dev];
 425 
 426   if (!codec_dev)
 427     return RET_ERROR (ENXIO);
 428 
 429   codec_dev--;
 430 
 431   devc = (ad1848_info *) audio_devs[codec_dev]->devc;
 432 
 433   if (((cmd >> 8) & 0xff) == 'M')
 434     {
 435       if (cmd & IOC_IN)
 436         switch (cmd & 0xff)
 437           {
 438           case SOUND_MIXER_RECSRC:
 439             return IOCTL_OUT (arg, ad1848_set_recmask (devc, IOCTL_IN (arg)));
 440             break;
 441 
 442           default:
 443             return IOCTL_OUT (arg, ad1848_mixer_set (devc, cmd & 0xff, IOCTL_IN (arg)));
 444           }
 445       else
 446         switch (cmd & 0xff)     /*
 447                                  * Return parameters
 448                                  */
 449           {
 450 
 451           case SOUND_MIXER_RECSRC:
 452             return IOCTL_OUT (arg, devc->recmask);
 453             break;
 454 
 455           case SOUND_MIXER_DEVMASK:
 456             return IOCTL_OUT (arg, devc->supported_devices);
 457             break;
 458 
 459           case SOUND_MIXER_STEREODEVS:
 460             return IOCTL_OUT (arg, devc->supported_devices &
 461                               ~(SOUND_MASK_SPEAKER | SOUND_MASK_IMIX));
 462             break;
 463 
 464           case SOUND_MIXER_RECMASK:
 465             return IOCTL_OUT (arg, devc->supported_rec_devices);
 466             break;
 467 
 468           case SOUND_MIXER_CAPS:
 469             return IOCTL_OUT (arg, SOUND_CAP_EXCL_INPUT);
 470             break;
 471 
 472           default:
 473             return IOCTL_OUT (arg, ad1848_mixer_get (devc, cmd & 0xff));
 474           }
 475     }
 476   else
 477     return RET_ERROR (EINVAL);
 478 }
 479 
 480 static struct audio_operations ad1848_pcm_operations[MAX_AUDIO_DEV] =
 481 {
 482   {
 483     "Generic AD1848 codec",
 484     DMA_AUTOMODE,
 485     AFMT_U8,                    /* Will be set later */
 486     NULL,
 487     ad1848_open,
 488     ad1848_close,
 489     ad1848_output_block,
 490     ad1848_start_input,
 491     ad1848_ioctl,
 492     ad1848_prepare_for_IO,
 493     ad1848_prepare_for_IO,
 494     ad1848_reset,
 495     ad1848_halt,
 496     NULL,
 497     NULL
 498   }};
 499 
 500 static struct mixer_operations ad1848_mixer_operations =
 501 {
 502   "AD1848/CS4248/CS4231",
 503   ad1848_mixer_ioctl
 504 };
 505 
 506 static int
 507 ad1848_open (int dev, int mode)
     /*  */
 508 {
 509   int             err;
 510   ad1848_info    *devc = NULL;
 511   unsigned long   flags;
 512 
 513   DEB (printk ("ad1848_open(int mode = %X)\n", mode));
 514 
 515   if (dev < 0 || dev >= num_audiodevs)
 516     return RET_ERROR (ENXIO);
 517 
 518   devc = (ad1848_info *) audio_devs[dev]->devc;
 519 
 520   DISABLE_INTR (flags);
 521   if (devc->opened)
 522     {
 523       RESTORE_INTR (flags);
 524       printk ("ad1848: Already opened\n");
 525       return RET_ERROR (EBUSY);
 526     }
 527 
 528   if (devc->irq)                /* Not managed by another driver */
 529     if ((err = snd_set_irq_handler (devc->irq, ad1848_interrupt,
 530                                     audio_devs[dev]->name)) < 0)
 531       {
 532         printk ("ad1848: IRQ in use\n");
 533         RESTORE_INTR (flags);
 534         return err;
 535       }
 536 
 537 /*
 538  * Allocate DMA
 539  */
 540 
 541   if (mode & OPEN_WRITE)
 542     audio_devs[dev]->dmachan = devc->dma_playback;
 543   else
 544     audio_devs[dev]->dmachan = devc->dma_capture;
 545 
 546   if (DMAbuf_open_dma (dev) < 0)
 547     {
 548       RESTORE_INTR (flags);
 549       if (devc->irq)            /* Don't leave IRQ reserved */
 550         snd_release_irq (devc->irq);
 551 
 552       printk ("ad1848: DMA in use\n");
 553       return RET_ERROR (EBUSY);
 554     }
 555 
 556   devc->dual_dma = 0;
 557 
 558   if (devc->dma_capture != devc->dma_playback && mode == OPEN_READWRITE)
 559     {
 560       devc->dual_dma = 1;
 561 
 562       if (ALLOC_DMA_CHN (devc->dma_capture, "Sound System (capture)"))
 563         {
 564           if (devc->irq)        /* Don't leave IRQ reserved */
 565             snd_release_irq (devc->irq);
 566           DMAbuf_close_dma (dev);
 567           return RET_ERROR (EBUSY);
 568         }
 569     }
 570 
 571   devc->intr_active = 0;
 572   devc->opened = 1;
 573   RESTORE_INTR (flags);
 574 /*
 575  * Mute output until the playback really starts. This decreases clicking.
 576  */
 577   ad_mute (devc);
 578 
 579   return 0;
 580 }
 581 
 582 static void
 583 ad1848_close (int dev)
     /*  */
 584 {
 585   unsigned long   flags;
 586   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 587 
 588   DEB (printk ("ad1848_close(void)\n"));
 589 
 590   DISABLE_INTR (flags);
 591 
 592   devc->intr_active = 0;
 593   if (devc->irq)                /* Not managed by another driver */
 594     snd_release_irq (devc->irq);
 595   ad1848_reset (dev);
 596   DMAbuf_close_dma (dev);
 597 
 598   if (devc->dual_dma)           /* Release the second DMA channel */
 599     {
 600       if (audio_devs[dev]->dmachan == devc->dma_playback)
 601         RELEASE_DMA_CHN (devc->dma_capture);
 602       else
 603         RELEASE_DMA_CHN (devc->dma_playback);
 604     }
 605 
 606   devc->opened = 0;
 607 
 608   ad_unmute (devc);
 609   RESTORE_INTR (flags);
 610 }
 611 
 612 static int
 613 set_speed (ad1848_info * devc, int arg)
     /*  */
 614 {
 615   /*
 616      * The sampling speed is encoded in the least significant nible of I8. The
 617      * LSB selects the clock source (0=24.576 MHz, 1=16.9344 Mhz) and other
 618      * three bits select the divisor (indirectly):
 619      *
 620      * The available speeds are in the following table. Keep the speeds in
 621      * the increasing order.
 622    */
 623   typedef struct
 624   {
 625     int             speed;
 626     unsigned char   bits;
 627   }
 628   speed_struct;
 629 
 630   static speed_struct speed_table[] =
 631   {
 632     {5510, (0 << 1) | 1},
 633     {5510, (0 << 1) | 1},
 634     {6620, (7 << 1) | 1},
 635     {8000, (0 << 1) | 0},
 636     {9600, (7 << 1) | 0},
 637     {11025, (1 << 1) | 1},
 638     {16000, (1 << 1) | 0},
 639     {18900, (2 << 1) | 1},
 640     {22050, (3 << 1) | 1},
 641     {27420, (2 << 1) | 0},
 642     {32000, (3 << 1) | 0},
 643     {33075, (6 << 1) | 1},
 644     {37800, (4 << 1) | 1},
 645     {44100, (5 << 1) | 1},
 646     {48000, (6 << 1) | 0}
 647   };
 648 
 649   int             i, n, selected = -1;
 650 
 651   n = sizeof (speed_table) / sizeof (speed_struct);
 652 
 653   if (arg < speed_table[0].speed)
 654     selected = 0;
 655   if (arg > speed_table[n - 1].speed)
 656     selected = n - 1;
 657 
 658   for (i = 1 /*really */ ; selected == -1 && i < n; i++)
 659     if (speed_table[i].speed == arg)
 660       selected = i;
 661     else if (speed_table[i].speed > arg)
 662       {
 663         int             diff1, diff2;
 664 
 665         diff1 = arg - speed_table[i - 1].speed;
 666         diff2 = speed_table[i].speed - arg;
 667 
 668         if (diff1 < diff2)
 669           selected = i - 1;
 670         else
 671           selected = i;
 672       }
 673 
 674   if (selected == -1)
 675     {
 676       printk ("ad1848: Can't find speed???\n");
 677       selected = 3;
 678     }
 679 
 680   devc->speed = speed_table[selected].speed;
 681   devc->speed_bits = speed_table[selected].bits;
 682   return devc->speed;
 683 }
 684 
 685 static int
 686 set_channels (ad1848_info * devc, int arg)
     /*  */
 687 {
 688   if (arg != 1 && arg != 2)
 689     return devc->channels;
 690 
 691   devc->channels = arg;
 692   return arg;
 693 }
 694 
 695 static int
 696 set_format (ad1848_info * devc, int arg)
     /*  */
 697 {
 698 
 699   static struct format_tbl
 700   {
 701     int             format;
 702     unsigned char   bits;
 703   }
 704   format2bits[] =
 705   {
 706     {
 707       0, 0
 708     }
 709     ,
 710     {
 711       AFMT_MU_LAW, 1
 712     }
 713     ,
 714     {
 715       AFMT_A_LAW, 3
 716     }
 717     ,
 718     {
 719       AFMT_IMA_ADPCM, 5
 720     }
 721     ,
 722     {
 723       AFMT_U8, 0
 724     }
 725     ,
 726     {
 727       AFMT_S16_LE, 2
 728     }
 729     ,
 730     {
 731       AFMT_S16_BE, 6
 732     }
 733     ,
 734     {
 735       AFMT_S8, 0
 736     }
 737     ,
 738     {
 739       AFMT_U16_LE, 0
 740     }
 741     ,
 742     {
 743       AFMT_U16_BE, 0
 744     }
 745   };
 746   int             i, n = sizeof (format2bits) / sizeof (struct format_tbl);
 747 
 748   if (!(arg & ad_format_mask[devc->mode]))
 749     arg = AFMT_U8;
 750 
 751   devc->audio_format = arg;
 752 
 753   for (i = 0; i < n; i++)
 754     if (format2bits[i].format == arg)
 755       {
 756         if ((devc->format_bits = format2bits[i].bits) == 0)
 757           return devc->audio_format = AFMT_U8;  /* Was not supported */
 758 
 759         return arg;
 760       }
 761 
 762   /* Still hanging here. Something must be terribly wrong */
 763   devc->format_bits = 0;
 764   return devc->audio_format = AFMT_U8;
 765 }
 766 
 767 static int
 768 ad1848_ioctl (int dev, unsigned int cmd, unsigned int arg, int local)
     /*  */
 769 {
 770   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 771 
 772   switch (cmd)
 773     {
 774     case SOUND_PCM_WRITE_RATE:
 775       if (local)
 776         return set_speed (devc, arg);
 777       return IOCTL_OUT (arg, set_speed (devc, IOCTL_IN (arg)));
 778 
 779     case SOUND_PCM_READ_RATE:
 780       if (local)
 781         return devc->speed;
 782       return IOCTL_OUT (arg, devc->speed);
 783 
 784     case SNDCTL_DSP_STEREO:
 785       if (local)
 786         return set_channels (devc, arg + 1) - 1;
 787       return IOCTL_OUT (arg, set_channels (devc, IOCTL_IN (arg) + 1) - 1);
 788 
 789     case SOUND_PCM_WRITE_CHANNELS:
 790       if (local)
 791         return set_channels (devc, arg);
 792       return IOCTL_OUT (arg, set_channels (devc, IOCTL_IN (arg)));
 793 
 794     case SOUND_PCM_READ_CHANNELS:
 795       if (local)
 796         return devc->channels;
 797       return IOCTL_OUT (arg, devc->channels);
 798 
 799     case SNDCTL_DSP_SAMPLESIZE:
 800       if (local)
 801         return set_format (devc, arg);
 802       return IOCTL_OUT (arg, set_format (devc, IOCTL_IN (arg)));
 803 
 804     case SOUND_PCM_READ_BITS:
 805       if (local)
 806         return devc->audio_format;
 807       return IOCTL_OUT (arg, devc->audio_format);
 808 
 809     default:;
 810     }
 811   return RET_ERROR (EINVAL);
 812 }
 813 
 814 static void
 815 ad1848_output_block (int dev, unsigned long buf, int count, int intrflag, int dma_restart)
     /*  */
 816 {
 817   unsigned long   flags, cnt;
 818   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 819 
 820   cnt = count;
 821 
 822   audio_devs[dev]->dmachan = devc->dma_playback;
 823 
 824   if (devc->audio_format == AFMT_IMA_ADPCM)
 825     {
 826       cnt /= 4;
 827     }
 828   else
 829     {
 830       if (devc->audio_format & (AFMT_S16_LE | AFMT_S16_BE))     /* 16 bit data */
 831         cnt >>= 1;
 832     }
 833   if (devc->channels > 1)
 834     cnt >>= 1;
 835   cnt--;
 836 
 837   if (audio_devs[dev]->flags & DMA_AUTOMODE &&
 838       intrflag &&
 839       cnt == devc->xfer_count)
 840     {
 841       devc->irq_mode = IMODE_OUTPUT;
 842       devc->intr_active = 1;
 843       return;                   /*
 844                                  * Auto DMA mode on. No need to react
 845                                  */
 846     }
 847   DISABLE_INTR (flags);
 848 
 849   if (dma_restart)
 850     {
 851       /* ad1848_halt (dev); */
 852       DMAbuf_start_dma (dev, buf, count, DMA_MODE_WRITE);
 853     }
 854 
 855   ad_enter_MCE (devc);
 856 
 857   ad_write (devc, 15, (unsigned char) (cnt & 0xff));
 858   ad_write (devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
 859 
 860   if (devc->dma_playback == devc->dma_capture)
 861     {
 862       ad_write (devc, 9, 0x0d); /*
 863                                  * Playback enable, single DMA channel mode,
 864                                  * auto calibration on.
 865                                  */
 866     }
 867   else
 868     {
 869       ad_write (devc, 9, 0x09); /*
 870                                  * Playback enable, dual DMA channel mode.
 871                                  * auto calibration on.
 872                                  */
 873     }
 874 
 875   ad_leave_MCE (devc);          /*
 876                                  * Starts the calibration process and
 877                                  * enters playback mode after it.
 878                                  */
 879   ad_unmute (devc);
 880 
 881   devc->xfer_count = cnt;
 882   devc->irq_mode = IMODE_OUTPUT;
 883   devc->intr_active = 1;
 884   INB (io_Status (devc));
 885   OUTB (0, io_Status (devc));   /* Clear pending interrupts */
 886   RESTORE_INTR (flags);
 887 
 888 }
 889 
 890 static void
 891 ad1848_start_input (int dev, unsigned long buf, int count, int intrflag, int dma_restart)
     /*  */
 892 {
 893   unsigned long   flags, cnt;
 894   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 895 
 896   audio_devs[dev]->dmachan = devc->dma_capture;
 897 
 898   cnt = count;
 899   if (devc->audio_format == AFMT_IMA_ADPCM)
 900     {
 901       cnt /= 4;
 902     }
 903   else
 904     {
 905       if (devc->audio_format & (AFMT_S16_LE | AFMT_S16_BE))     /* 16 bit data */
 906         cnt >>= 1;
 907     }
 908   if (devc->channels > 1)
 909     cnt >>= 1;
 910   cnt--;
 911 
 912   if (audio_devs[dev]->flags & DMA_AUTOMODE &&
 913       intrflag &&
 914       cnt == devc->xfer_count)
 915     {
 916       devc->irq_mode = IMODE_INPUT;
 917       devc->intr_active = 1;
 918       return;                   /*
 919                                  * Auto DMA mode on. No need to react
 920                                  */
 921     }
 922   DISABLE_INTR (flags);
 923 
 924   if (dma_restart)
 925     {
 926       /* ad1848_halt (dev); */
 927       DMAbuf_start_dma (dev, buf, count, DMA_MODE_READ);
 928     }
 929 
 930   ad_enter_MCE (devc);
 931 
 932   if (devc->dma_playback == devc->dma_capture)  /* Single DMA channel mode */
 933     {
 934       ad_write (devc, 15, (unsigned char) (cnt & 0xff));
 935       ad_write (devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
 936 
 937       ad_write (devc, 9, 0x0e); /*
 938                                  * Capture enable, single DMA channel mode,
 939                                  * auto calibration on.
 940                                  */
 941     }
 942   else
 943     /* Dual DMA channel mode */
 944     {
 945       ad_write (devc, 31, (unsigned char) (cnt & 0xff));
 946       ad_write (devc, 30, (unsigned char) ((cnt >> 8) & 0xff));
 947 
 948       ad_write (devc, 9, 0x0a); /*
 949                                  * Capture enable, dual DMA channel mode,
 950                                  * auto calibration on.
 951                                  */
 952     }
 953 
 954   ad_leave_MCE (devc);          /*
 955                                  * Starts the calibration process and
 956                                  * enters playback mode after it.
 957                                  */
 958   ad_unmute (devc);
 959 
 960   devc->xfer_count = cnt;
 961   devc->irq_mode = IMODE_INPUT;
 962   devc->intr_active = 1;
 963   INB (io_Status (devc));
 964   OUTB (0, io_Status (devc));   /* Clear interrupt status */
 965   RESTORE_INTR (flags);
 966 }
 967 
 968 static int
 969 ad1848_prepare_for_IO (int dev, int bsize, int bcount)
     /*  */
 970 {
 971   int             timeout;
 972   unsigned char   fs;
 973   unsigned long   flags;
 974   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 975 
 976   DISABLE_INTR (flags);
 977   ad_enter_MCE (devc);          /* Enables changes to the format select reg */
 978   fs = devc->speed_bits | (devc->format_bits << 5);
 979 
 980   if (devc->channels > 1)
 981     fs |= 0x10;
 982 
 983   ad_write (devc, 8, fs);
 984   /*
 985    * Write to I8 starts resyncronization. Wait until it completes.
 986    */
 987   timeout = 10000;
 988   while (timeout > 0 && INB (devc->base) == 0x80)
 989     timeout--;
 990 
 991   /*
 992      * If mode == 2 (CS4231), set I28 also. It's the capture format register.
 993    */
 994   if (devc->mode == 2)
 995     {
 996       ad_write (devc, 28, fs);
 997 
 998       /*
 999          * Write to I28 starts resyncronization. Wait until it completes.
1000        */
1001       timeout = 10000;
1002       while (timeout > 0 && INB (devc->base) == 0x80)
1003         timeout--;
1004 
1005     }
1006 
1007   ad_leave_MCE (devc);          /*
1008                                  * Starts the calibration process.
1009                                  */
1010   RESTORE_INTR (flags);
1011   devc->xfer_count = 0;
1012   return 0;
1013 }
1014 
1015 static void
1016 ad1848_reset (int dev)
     /*  */
1017 {
1018   ad1848_halt (dev);
1019 }
1020 
1021 static void
1022 ad1848_halt (int dev)
     /*  */
1023 {
1024   ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1025 
1026   ad_mute (devc);
1027   ad_write (devc, 9, ad_read (devc, 9) & ~0x03);        /* Stop DMA */
1028   OUTB (0, io_Status (devc));   /* Clear interrupt status */
1029 
1030   ad_enter_MCE (devc);
1031   OUTB (0, io_Status (devc));   /* Clear interrupt status */
1032   ad_write (devc, 15, 0);       /* Clear DMA counter */
1033   ad_write (devc, 14, 0);       /* Clear DMA counter */
1034 
1035   if (devc->mode == 2)
1036     {
1037       ad_write (devc, 30, 0);   /* Clear DMA counter */
1038       ad_write (devc, 31, 0);   /* Clear DMA counter */
1039     }
1040 
1041   ad_write (devc, 9, ad_read (devc, 9) & ~0x03);        /* Stop DMA */
1042 
1043   OUTB (0, io_Status (devc));   /* Clear interrupt status */
1044   OUTB (0, io_Status (devc));   /* Clear interrupt status */
1045   ad_leave_MCE (devc);
1046 
1047   /* DMAbuf_reset_dma (dev); */
1048 }
1049 
1050 int
1051 ad1848_detect (int io_base)
     /*  */
1052 {
1053 
1054   unsigned char   tmp;
1055   int             i;
1056   ad1848_info    *devc = &dev_info[nr_ad1848_devs];
1057   unsigned char   tmp1 = 0xff, tmp2 = 0xff;
1058 
1059   if (nr_ad1848_devs >= MAX_AUDIO_DEV)
1060     {
1061       DDB (printk ("ad1848 detect error - step 0\n"));
1062       return 0;
1063     }
1064 
1065   devc->base = io_base;
1066   devc->MCE_bit = 0x40;
1067   devc->irq = 0;
1068   devc->dma_capture = 0;
1069   devc->dma_playback = 0;
1070   devc->opened = 0;
1071   devc->chip_name = "AD1848";
1072   devc->mode = 1;               /* MODE1 = original AD1848 */
1073 
1074   /*
1075      * Check that the I/O address is in use.
1076      *
1077      * The bit 0x80 of the base I/O port is known to be 0 after the
1078      * chip has performed it's power on initialization. Just assume
1079      * this has happened before the OS is starting.
1080      *
1081      * If the I/O address is unused, it typically returns 0xff.
1082    */
1083 
1084   if ((INB (devc->base) & 0x80) != 0x00)        /* Not a AD1884 */
1085     {
1086       DDB (printk ("ad1848 detect error - step A\n"));
1087       return 0;
1088     }
1089 
1090   /*
1091      * Test if it's possible to change contents of the indirect registers.
1092      * Registers 0 and 1 are ADC volume registers. The bit 0x10 is read only
1093      * so try to avoid using it.
1094    */
1095 
1096   ad_write (devc, 0, 0xaa);
1097   ad_write (devc, 1, 0x45);     /* 0x55 with bit 0x10 clear */
1098 
1099   if ((tmp1 = ad_read (devc, 0)) != 0xaa || (tmp2 = ad_read (devc, 1)) != 0x45)
1100     {
1101       DDB (printk ("ad1848 detect error - step B (%x/%x)\n", tmp1, tmp2));
1102       return 0;
1103     }
1104 
1105   ad_write (devc, 0, 0x45);
1106   ad_write (devc, 1, 0xaa);
1107 
1108   if ((tmp1 = ad_read (devc, 0)) != 0x45 || (tmp2 = ad_read (devc, 1)) != 0xaa)
1109     {
1110       DDB (printk ("ad1848 detect error - step C (%x/%x)\n", tmp1, tmp2));
1111       return 0;
1112     }
1113 
1114   /*
1115      * The indirect register I12 has some read only bits. Lets
1116      * try to change them.
1117    */
1118 
1119   tmp = ad_read (devc, 12);
1120   ad_write (devc, 12, (~tmp) & 0x0f);
1121 
1122   if ((tmp & 0x0f) != ((tmp1 = ad_read (devc, 12)) & 0x0f))
1123     {
1124       DDB (printk ("ad1848 detect error - step D (%x)\n", tmp1));
1125       return 0;
1126     }
1127 
1128   /*
1129      * NOTE! Last 4 bits of the reg I12 tell the chip revision.
1130      *   0x01=RevB and 0x0A=RevC.
1131    */
1132 
1133   /*
1134      * The original AD1848/CS4248 has just 15 indirect registers. This means
1135      * that I0 and I16 should return the same value (etc.).
1136      * Ensure that the Mode2 enable bit of I12 is 0. Otherwise this test fails
1137      * with CS4231.
1138    */
1139 
1140   ad_write (devc, 12, 0);       /* Mode2=disabled */
1141 
1142   for (i = 0; i < 16; i++)
1143     if ((tmp1 = ad_read (devc, i)) != (tmp2 = ad_read (devc, i + 16)))
1144       {
1145         DDB (printk ("ad1848 detect error - step F(%d/%x/%x)\n", i, tmp1, tmp2));
1146         return 0;
1147       }
1148 
1149   /*
1150      * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit (0x40).
1151      * The bit 0x80 is always 1 in CS4248 and CS4231.
1152    */
1153 
1154   ad_write (devc, 12, 0x40);    /* Set mode2, clear 0x80 */
1155 
1156   tmp1 = ad_read (devc, 12);
1157   if (tmp1 & 0x80)
1158     devc->chip_name = "CS4248"; /* Our best knowledge just now */
1159 
1160   if ((tmp1 & 0xc0) == (0x80 | 0x40))
1161     {
1162       /*
1163          *      CS4231 detected - is it?
1164          *
1165          *      Verify that setting I0 doesn't change I16.
1166        */
1167       ad_write (devc, 16, 0);   /* Set I16 to known value */
1168 
1169       ad_write (devc, 0, 0x45);
1170       if ((tmp1 = ad_read (devc, 16)) != 0x45)  /* No change -> CS4231? */
1171         {
1172 
1173           ad_write (devc, 0, 0xaa);
1174           if ((tmp1 = ad_read (devc, 16)) == 0xaa)      /* Rotten bits? */
1175             {
1176               DDB (printk ("ad1848 detect error - step H(%x)\n", tmp1));
1177               return 0;
1178             }
1179 
1180           /*
1181              * Verify that some bits of I25 are read only.
1182            */
1183 
1184           tmp1 = ad_read (devc, 25);    /* Original bits */
1185           ad_write (devc, 25, ~tmp1);   /* Invert all bits */
1186           if ((ad_read (devc, 25) & 0xe7) == (tmp1 & 0xe7))
1187             {
1188               /*
1189                *      It's at least CS4231
1190                */
1191               devc->chip_name = "CS4231";
1192 
1193 #ifdef MOZART_PORT
1194               if (devc->base != MOZART_PORT + 4)
1195 #endif
1196                 devc->mode = 2;
1197 
1198               /*
1199                * It could be an AD1845 or CS4231A as well.
1200                * CS4231 and AD1845 report the same revision info in I25
1201                * while the CS4231A reports different.
1202                */
1203 
1204               if ((ad_read (devc, 25) & 0xe7) == 0xa0)
1205                 {
1206                   devc->chip_name = "CS4231A";
1207                 }
1208               else if ((ad_read (devc, 25) & 0xe7) == 0x80)
1209                 {
1210                   /* 
1211                    * It must be a CS4231 or AD1845. The register I23 of
1212                    * CS4231 is undefined and it appears to be read only.
1213                    * AD1845 uses I23 for setting sample rate. Assume
1214                    * the chip is AD1845 if I23 is changeable.
1215                    */
1216 
1217                   unsigned char   tmp = ad_read (devc, 23);
1218 
1219                   ad_write (devc, 23, ~tmp);
1220                   if (ad_read (devc, 23) != tmp)        /* AD1845 ? */
1221                     {
1222                       devc->chip_name = "AD1845";
1223                     }
1224 
1225                   ad_write (devc, 23, tmp);     /* Restore */
1226                 }
1227 
1228               /* Otherwise behave just as if the chip is a CS4231 */
1229             }
1230           ad_write (devc, 25, tmp1);    /* Restore bits */
1231         }
1232     }
1233 
1234   return 1;
1235 }
1236 
1237 void
1238 ad1848_init (char *name, int io_base, int irq, int dma_playback, int dma_capture)
     /*  */
1239 {
1240   /*
1241      * NOTE! If irq < 0, there is another driver which has allocated the IRQ
1242      *   so that this driver doesn't need to allocate/deallocate it.
1243      *   The actually used IRQ is ABS(irq).
1244    */
1245 
1246   /*
1247      * Initial values for the indirect registers of CS4248/AD1848.
1248    */
1249   static int      init_values[] =
1250   {
1251     0xa8, 0xa8, 0x08, 0x08, 0x08, 0x08, 0x80, 0x80,
1252     0x00, 0x08, 0x02, 0x00, 0x8a, 0x01, 0x00, 0x00,
1253 
1254   /* Positions 16 to 31 just for CS4231 */
1255     0x80, 0x00, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00,
1256     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1257   };
1258   int             i, my_dev;
1259   ad1848_info    *devc = &dev_info[nr_ad1848_devs];
1260 
1261   if (!ad1848_detect (io_base))
1262     return;
1263 
1264   devc->irq = (irq > 0) ? irq : 0;
1265   devc->dma_playback = dma_playback;
1266 
1267   if (devc->mode == 2)
1268     devc->dma_capture = dma_capture;
1269   else
1270     devc->dma_capture = dma_playback;   /* Use just single DMA */
1271 
1272   devc->opened = 0;
1273 
1274   if (nr_ad1848_devs != 0)
1275     {
1276       memcpy ((char *) &ad1848_pcm_operations[nr_ad1848_devs],
1277               (char *) &ad1848_pcm_operations[0],
1278               sizeof (struct audio_operations));
1279     }
1280 
1281   for (i = 0; i < 16; i++)
1282     ad_write (devc, i, init_values[i]);
1283 
1284   ad_mute (devc);               /* Initialize some variables */
1285   ad_unmute (devc);             /* Leave it unmuted now */
1286 
1287   if (devc->mode == 2)
1288     {
1289       ad_write (devc, 12, ad_read (devc, 12) | 0x40);   /* Mode2 = enabled */
1290       for (i = 16; i < 32; i++)
1291         ad_write (devc, i, init_values[i]);
1292     }
1293 
1294   OUTB (0, io_Status (devc));   /* Clear pending interrupts */
1295 
1296   if (name[0] != 0)
1297     sprintf (ad1848_pcm_operations[nr_ad1848_devs].name,
1298              "%s (%s)", name, devc->chip_name);
1299   else
1300     sprintf (ad1848_pcm_operations[nr_ad1848_devs].name,
1301              "Generic audio codec (%s)", devc->chip_name);
1302 
1303   printk (" <%s>", ad1848_pcm_operations[nr_ad1848_devs].name);
1304 
1305   if (num_audiodevs < MAX_AUDIO_DEV)
1306     {
1307       audio_devs[my_dev = num_audiodevs++] = &ad1848_pcm_operations[nr_ad1848_devs];
1308       if (irq > 0)
1309         irq2dev[irq] = my_dev;
1310       else if (irq < 0)
1311         irq2dev[-irq] = my_dev;
1312 
1313       audio_devs[my_dev]->dmachan = dma_playback;
1314       audio_devs[my_dev]->buffcount = 1;
1315       audio_devs[my_dev]->buffsize = DSP_BUFFSIZE * 2;
1316       audio_devs[my_dev]->devc = devc;
1317       audio_devs[my_dev]->format_mask = ad_format_mask[devc->mode];
1318       nr_ad1848_devs++;
1319 
1320       /*
1321          * Toggle the MCE bit. It completes the initialization phase.
1322        */
1323 
1324       ad_enter_MCE (devc);      /* In case the bit was off */
1325       ad_leave_MCE (devc);
1326 
1327       if (num_mixers < MAX_MIXER_DEV)
1328         {
1329           mixer2codec[num_mixers] = my_dev + 1;
1330           audio_devs[my_dev]->mixer_dev = num_mixers;
1331           mixer_devs[num_mixers++] = &ad1848_mixer_operations;
1332           ad1848_mixer_reset (devc);
1333         }
1334     }
1335   else
1336     printk ("AD1848: Too many PCM devices available\n");
1337 }
1338 
1339 void
1340 ad1848_interrupt (INT_HANDLER_PARMS (irq, dummy))
     /*  */
1341 {
1342   unsigned char   status;
1343   ad1848_info    *devc;
1344   int             dev;
1345 
1346   if (irq < 0 || irq > 15)
1347     return;                     /* Bogus irq */
1348   dev = irq2dev[irq];
1349   if (dev < 0 || dev >= num_audiodevs)
1350     return;                     /* Bogus dev */
1351 
1352   devc = (ad1848_info *) audio_devs[dev]->devc;
1353   status = INB (io_Status (devc));
1354 
1355   if (status == 0x80)
1356     printk ("ad1848_interrupt: Why?\n");
1357 
1358   if (status & 0x01)
1359     {
1360       if (devc->opened && devc->irq_mode == IMODE_OUTPUT)
1361         {
1362           DMAbuf_outputintr (dev, 1);
1363         }
1364 
1365       if (devc->opened && devc->irq_mode == IMODE_INPUT)
1366         DMAbuf_inputintr (dev);
1367     }
1368 
1369   OUTB (0, io_Status (devc));   /* Clear interrupt status */
1370 
1371   status = INB (io_Status (devc));
1372   if (status == 0x80 || status & 0x01)
1373     {
1374       printk ("ad1848: Problems when clearing interrupt, status=%x\n", status);
1375       OUTB (0, io_Status (devc));       /* Try again */
1376     }
1377 }
1378 
1379 /*
1380  * Some extra code for the MS Sound System
1381  */
1382 
1383 int
1384 probe_ms_sound (struct address_info *hw_config)
     /*  */
1385 {
1386 #if !defined(EXCLUDE_AEDSP16) && defined(AEDSP16_MSS)
1387   /*
1388      * Initialize Audio Excel DSP 16 to MSS: before any operation
1389      * we must enable MSS I/O ports.
1390    */
1391 
1392   InitAEDSP16_MSS (hw_config);
1393 #endif
1394 
1395   /*
1396      * Check if the IO port returns valid signature. The original MS Sound
1397      * system returns 0x04 while some cards (AudioTriX Pro for example)
1398      * return 0x00.
1399    */
1400 
1401   if ((INB (hw_config->io_base + 3) & 0x3f) != 0x04 &&
1402       (INB (hw_config->io_base + 3) & 0x3f) != 0x00)
1403     {
1404       DDB (printk ("No MSS signature detected on port 0x%x (0x%x)\n",
1405                    hw_config->io_base, INB (hw_config->io_base + 3)));
1406       return 0;
1407     }
1408 
1409   if (hw_config->irq > 11)
1410     {
1411       printk ("MSS: Bad IRQ %d\n", hw_config->irq);
1412       return 0;
1413     }
1414 
1415   if (hw_config->dma != 0 && hw_config->dma != 1 && hw_config->dma != 3)
1416     {
1417       printk ("MSS: Bad DMA %d\n", hw_config->dma);
1418       return 0;
1419     }
1420 
1421   /*
1422      * Check that DMA0 is not in use with a 8 bit board.
1423    */
1424 
1425   if (hw_config->dma == 0 && INB (hw_config->io_base + 3) & 0x80)
1426     {
1427       printk ("MSS: Can't use DMA0 with a 8 bit card/slot\n");
1428       return 0;
1429     }
1430 
1431   if (hw_config->irq > 7 && hw_config->irq != 9 && INB (hw_config->io_base + 3) & 0x80)
1432     {
1433       printk ("MSS: Can't use IRQ%d with a 8 bit card/slot\n", hw_config->irq);
1434       return 0;
1435     }
1436 
1437   return ad1848_detect (hw_config->io_base + 4);
1438 }
1439 
1440 long
1441 attach_ms_sound (long mem_start, struct address_info *hw_config)
     /*  */
1442 {
1443   static char     interrupt_bits[12] =
1444   {
1445     -1, -1, -1, -1, -1, -1, -1, 0x08, -1, 0x10, 0x18, 0x20
1446   };
1447   char            bits;
1448 
1449   static char     dma_bits[4] =
1450   {
1451     1, 2, 0, 3
1452   };
1453 
1454   int             config_port = hw_config->io_base + 0, version_port = hw_config->io_base + 3;
1455 
1456   if (!ad1848_detect (hw_config->io_base + 4))
1457     return mem_start;
1458 
1459   /*
1460      * Set the IRQ and DMA addresses.
1461    */
1462 
1463   bits = interrupt_bits[hw_config->irq];
1464   if (bits == -1)
1465     return mem_start;
1466 
1467   OUTB (bits | 0x40, config_port);
1468   if ((INB (version_port) & 0x40) == 0)
1469     printk ("[IRQ Conflict?]");
1470 
1471   OUTB (bits | dma_bits[hw_config->dma], config_port);  /* Write IRQ+DMA setup */
1472 
1473   ad1848_init ("MS Sound System", hw_config->io_base + 4,
1474                hw_config->irq,
1475                hw_config->dma,
1476                hw_config->dma);
1477   return mem_start;
1478 }
1479 
1480 #endif
/* */
root/drivers/sound/ad1848.c

DEFINITIONS
