This source file includes following definitions.
- pci_lookup_dev
- pci_strbioserr
- pci_strclass
- pci_strvendor
- pci_strdev
- burst_bridge
- sprint_dev_config
- get_pci_list
- pci_malloc
- scan_bus
- pci_init
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8
9 #include <linux/config.h>
10 #include <linux/types.h>
11 #include <linux/kernel.h>
12 #include <linux/bios32.h>
13 #include <linux/pci.h>
14 #include <linux/string.h>
15
16 #include <asm/page.h>
17
18 struct pci_bus pci_root;
19 struct pci_dev *pci_devices = 0;
20
21
22
23
24
25
26
27
28
29
30
31 #define DEVICE(vid,did,name) \
32 {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), 0xff}
33
34 #define BRIDGE(vid,did,name,bridge) \
35 {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), (bridge)}
36
37 struct pci_dev_info dev_info[] = {
38 DEVICE( NCR, NCR_53C810, "53c810"),
39 DEVICE( NCR, NCR_53C815, "53c815"),
40 DEVICE( NCR, NCR_53C820, "53c820"),
41 DEVICE( NCR, NCR_53C825, "53c825"),
42 DEVICE( ADAPTEC, ADAPTEC_2940, "2940"),
43 DEVICE( ADAPTEC, ADAPTEC_294x, "294x"),
44 DEVICE( ADAPTEC, ADAPTEC_7850, "AIC-7850"),
45 DEVICE( DPT, DPT, "SmartCache/Raid"),
46 DEVICE( S3, S3_864_1, "Vision 864-P"),
47 DEVICE( S3, S3_864_2, "Vision 864-P"),
48 DEVICE( S3, S3_868, "Vision 868"),
49 DEVICE( S3, S3_928, "Vision 928-P"),
50 DEVICE( S3, S3_964_1, "Vision 964-P"),
51 DEVICE( S3, S3_964_2, "Vision 964-P"),
52 DEVICE( S3, S3_811, "Trio32/Trio64"),
53 DEVICE( S3, S3_968, "Vision 968"),
54 DEVICE( OPTI, OPTI_82C822, "82C822"),
55 DEVICE( OPTI, OPTI_82C621, "82C621"),
56 DEVICE( OPTI, OPTI_82C557, "82C557"),
57 DEVICE( OPTI, OPTI_82C558, "82C558"),
58 BRIDGE( UMC, UMC_UM8881F, "UM8881F", 0x02),
59 BRIDGE( UMC, UMC_UM8891A, "UM8891A", 0x01),
60 DEVICE( UMC, UMC_UM8886F, "UM8886F"),
61 DEVICE( UMC, UMC_UM8886A, "UM8886A"),
62 DEVICE( UMC, UMC_UM8673F, "UM8673F"),
63 DEVICE( DEC, DEC_TULIP, "DC21040"),
64 DEVICE( DEC, DEC_TULIP_FAST, "DC21140"),
65 DEVICE( DEC, DEC_TULIP_PLUS, "DC21041"),
66 DEVICE( DEC, DEC_FDDI, "DEFPA"),
67 DEVICE( DEC, DEC_BRD, "DC21050"),
68 DEVICE( MATROX, MATROX_MGA_2, "Atlas PX2085"),
69 DEVICE( MATROX, MATROX_MGA_IMP, "MGA Impression"),
70 DEVICE( MATROX, MATROX_MIL ,"Millenium"),
71 DEVICE( INTEL, INTEL_82378, "82378IB"),
72 BRIDGE( INTEL, INTEL_82424, "82424ZX Saturn", 0x00),
73 DEVICE( INTEL, INTEL_82375, "82375EB"),
74 BRIDGE( INTEL, INTEL_82434, "82434LX Mercury/Neptune", 0x00),
75 DEVICE( INTEL, INTEL_82430, "82430ZX Aries"),
76 DEVICE( INTEL, INTEL_82437, "82437 Triton"),
77 DEVICE( INTEL, INTEL_82371, "82371 Triton"),
78 DEVICE( INTEL, INTEL_82438, "82438/82371"),
79 DEVICE( INTEL, INTEL_7116, "SAA7116"),
80 DEVICE( INTEL, INTEL_82865, "82865"),
81 DEVICE( INTEL, INTEL_P6, "Experimental P6 bridge"),
82 #if 0
83 DEVICE( SMC, SMC_37C665, "FDC 37C665"),
84 DEVICE( SMC, SMC_37C922, "FDC 37C922"),
85 #else
86 DEVICE( PCTECH, PCTECH_RZ1000, "RZ1000 (buggy)"),
87 #endif
88 DEVICE( ATI, ATI_68800, "68800AX"),
89 DEVICE( ATI, ATI_215CT222, "215CT222"),
90 DEVICE( ATI, ATI_210888GX, "210888GX"),
91 DEVICE( ATI, ATI_210888CX, "210888CX"),
92 DEVICE( WEITEK, WEITEK_P9000, "P9000"),
93 DEVICE( WEITEK, WEITEK_P9100, "P9100"),
94 DEVICE( CIRRUS, CIRRUS_5430, "GD 5430"),
95 DEVICE( CIRRUS, CIRRUS_5434_4, "GD 5434"),
96 DEVICE( CIRRUS, CIRRUS_5434_8, "GD 5434"),
97 DEVICE( CIRRUS, CIRRUS_6729, "CL 6729"),
98 DEVICE( CIRRUS, CIRRUS_7542, "CL 7542"),
99 DEVICE( BUSLOGIC, BUSLOGIC_946C, "946C"),
100 DEVICE( BUSLOGIC, BUSLOGIC_946C_2,"946C"),
101 DEVICE( N9, N9_I128, "Imagine 128"),
102 DEVICE( AI, AI_M1435, "M1435"),
103 DEVICE( AL, AL_M1445, "M1445"),
104 DEVICE( AL, AL_M1449, "M1449"),
105 DEVICE( AL, AL_M1451, "M1451"),
106 DEVICE( AL, AL_M1461, "M1461"),
107 DEVICE( AL, AL_M4803, "M4803"),
108 DEVICE( TSENG, TSENG_W32P_2, "ET4000W32P"),
109 DEVICE( TSENG, TSENG_W32P_b, "ET4000W32P rev B"),
110 DEVICE( TSENG, TSENG_W32P_c, "ET4000W32P rev C"),
111 DEVICE( TSENG, TSENG_W32P_d, "ET4000W32P rev D"),
112 DEVICE( CMD, CMD_640, "640 (buggy)"),
113 DEVICE( VISION, VISION_QD8500, "QD-8500"),
114 DEVICE( VISION, VISION_QD8580, "QD-8580"),
115 DEVICE( AMD, AMD_LANCE, "79C970"),
116 DEVICE( AMD, AMD_SCSI, "53C974"),
117 DEVICE( VLSI, VLSI_82C593, "82C593-FC1"),
118 DEVICE( VLSI, VLSI_82C592, "82C592-FC1"),
119 DEVICE( ADL, ADL_2301, "2301"),
120 DEVICE( SYMPHONY, SYMPHONY_101, "82C101"),
121 DEVICE( TRIDENT, TRIDENT_9420, "TG 9420"),
122 DEVICE( TRIDENT, TRIDENT_9440, "TG 9440"),
123 DEVICE( CONTAQ, CONTAQ_82C599, "82C599"),
124 DEVICE( NS, NS_87410, "87410"),
125 DEVICE( VIA, VIA_82C505, "VT 82C505"),
126 DEVICE( VIA, VIA_82C576, "VT 82C576 3V"),
127 DEVICE( VIA, VIA_82C561, "VT 82C561"),
128 DEVICE( SI, SI_496, "85C496"),
129 DEVICE( SI, SI_501, "85C501"),
130 DEVICE( SI, SI_503, "85C503"),
131 DEVICE( SI, SI_601, "85C601"),
132 DEVICE( LEADTEK, LEADTEK_805, "S3 805"),
133 DEVICE( IMS, IMS_8849, "8849"),
134 DEVICE( ZEINET, ZEINET_1221, "1221"),
135 DEVICE( EF, EF_ATM, "155P-MF1"),
136 DEVICE( HER, HER_STING, "Stingray"),
137 DEVICE( HER, HER_STINGARK, "Stingray ARK 2000PV"),
138 DEVICE( ATRONICS, ATRONICS_2015, "IDE-2015PL"),
139 DEVICE( CT, CT_65545, "65545"),
140 DEVICE( FD, FD_36C70, "TMC-18C30"),
141 DEVICE( WINBOND, WINBOND_83769, "W83769F"),
142 DEVICE( 3COM, 3COM_3C590, "3C590 10bT"),
143 DEVICE( 3COM, 3COM_3C595TX, "3C595 100bTX"),
144 DEVICE( 3COM, 3COM_3C595T4, "3C595 100bT4"),
145 DEVICE( 3COM, 3COM_3C595MII, "3C595 100b-MII"),
146 DEVICE( PROMISE, PROMISE_5300, "DC5030"),
147 DEVICE( QLOGIC, QLOGIC_ISP1020, "ISP1020"),
148 DEVICE( QLOGIC, QLOGIC_ISP1022, "ISP1022"),
149 DEVICE( X, X_AGX016, "ITT AGX016"),
150 DEVICE( VORTEX, VORTEX_GDT, "GDT 6000b"),
151 DEVICE( HP, HP_J2585A, "J2585A"),
152 DEVICE( MUTECH, MUTECH_MV1000, "MV-1000"),
153 DEVICE( TEKRAM, TEKRAM_DC290, "DC-290"),
154 DEVICE( IMAGINGTECH, IMAGINGTECH_ICPCI, "MVC IC-PCI"),
155 DEVICE( CYCLADES, CYCLADES_Y, "Cyclome-Y"),
156 DEVICE( PLX, PLX_9060, "PCI9060 i960 bridge")
157 };
158
159
160 #ifdef CONFIG_PCI_OPTIMIZE
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177 struct optimization_type {
178 const char *type;
179 const char *off;
180 const char *on;
181 } bridge_optimization[] = {
182 {"Cache L2", "write trough", "write back"},
183 {"CPU-PCI posted write", "off", "on"},
184 {"CPU-Memory posted write", "off", "on"},
185 {"PCI-Memory posted write", "off", "on"},
186 {"PCI burst", "off", "on"}
187 };
188
189 #define NUM_OPTIMIZATIONS \
190 (sizeof(bridge_optimization) / sizeof(bridge_optimization[0]))
191
192 struct bridge_mapping_type {
193 unsigned char addr;
194 unsigned char mask;
195 unsigned char value;
196 } bridge_mapping[] = {
197
198
199
200
201
202
203
204 {0x0 ,0x02 ,0x02 },
205 {0x53 ,0x02 ,0x02 },
206 {0x53 ,0x01 ,0x01 },
207 {0x54 ,0x01 ,0x01 },
208 {0x54 ,0x02 ,0x02 },
209
210
211
212
213
214 {0x50 ,0x10 ,0x00 },
215 {0x51 ,0x40 ,0x40 },
216 {0x0 ,0x0 ,0x0 },
217 {0x0 ,0x0 ,0x0 },
218 {0x0 ,0x0 ,0x0 },
219
220
221
222
223
224
225 {0x0 ,0x1 ,0x1 },
226 {0x0 ,0x2 ,0x0 },
227 {0x0 ,0x0 ,0x0 },
228 {0x0 ,0x0 ,0x0 },
229 {0x0 ,0x0 ,0x0 }
230 };
231
232 #endif
233
234
235
236
237
238
239 struct pci_dev_info *pci_lookup_dev(unsigned int vendor, unsigned int dev)
240 {
241 int i;
242
243 for (i = 0; i < sizeof(dev_info)/sizeof(dev_info[0]); ++i) {
244 if (dev_info[i].vendor == vendor &&
245 dev_info[i].device == dev)
246 {
247 return &dev_info[i];
248 }
249 }
250 return 0;
251 }
252
253
254 const char *pci_strbioserr (int error)
255 {
256 switch (error) {
257 case PCIBIOS_SUCCESSFUL: return "SUCCESSFUL";
258 case PCIBIOS_FUNC_NOT_SUPPORTED: return "FUNC_NOT_SUPPORTED";
259 case PCIBIOS_BAD_VENDOR_ID: return "SUCCESSFUL";
260 case PCIBIOS_DEVICE_NOT_FOUND: return "DEVICE_NOT_FOUND";
261 case PCIBIOS_BAD_REGISTER_NUMBER: return "BAD_REGISTER_NUMBER";
262 case PCIBIOS_SET_FAILED: return "SET_FAILED";
263 case PCIBIOS_BUFFER_TOO_SMALL: return "BUFFER_TOO_SMALL";
264 default: return "Unknown error status";
265 }
266 }
267
268
269 const char *pci_strclass (unsigned int class)
270 {
271 switch (class >> 8) {
272 case PCI_CLASS_NOT_DEFINED: return "Non-VGA device";
273 case PCI_CLASS_NOT_DEFINED_VGA: return "VGA compatible device";
274
275 case PCI_CLASS_STORAGE_SCSI: return "SCSI storage controller";
276 case PCI_CLASS_STORAGE_IDE: return "IDE interface";
277 case PCI_CLASS_STORAGE_FLOPPY: return "Floppy disk controller";
278 case PCI_CLASS_STORAGE_IPI: return "IPI bus controller";
279 case PCI_CLASS_STORAGE_RAID: return "RAID bus controller";
280 case PCI_CLASS_STORAGE_OTHER: return "Unknown mass storage controller";
281
282 case PCI_CLASS_NETWORK_ETHERNET: return "Ethernet controller";
283 case PCI_CLASS_NETWORK_TOKEN_RING: return "Token ring network controller";
284 case PCI_CLASS_NETWORK_FDDI: return "FDDI network controller";
285 case PCI_CLASS_NETWORK_ATM: return "ATM network controller";
286 case PCI_CLASS_NETWORK_OTHER: return "Network controller";
287
288 case PCI_CLASS_DISPLAY_VGA: return "VGA compatible controller";
289 case PCI_CLASS_DISPLAY_XGA: return "XGA compatible controller";
290 case PCI_CLASS_DISPLAY_OTHER: return "Display controller";
291
292 case PCI_CLASS_MULTIMEDIA_VIDEO: return "Multimedia video controller";
293 case PCI_CLASS_MULTIMEDIA_AUDIO: return "Multimedia audio controller";
294 case PCI_CLASS_MULTIMEDIA_OTHER: return "Multimedia controller";
295
296 case PCI_CLASS_MEMORY_RAM: return "RAM memory";
297 case PCI_CLASS_MEMORY_FLASH: return "FLASH memory";
298 case PCI_CLASS_MEMORY_OTHER: return "Memory";
299
300 case PCI_CLASS_BRIDGE_HOST: return "Host bridge";
301 case PCI_CLASS_BRIDGE_ISA: return "ISA bridge";
302 case PCI_CLASS_BRIDGE_EISA: return "EISA bridge";
303 case PCI_CLASS_BRIDGE_MC: return "MicroChannel bridge";
304 case PCI_CLASS_BRIDGE_PCI: return "PCI bridge";
305 case PCI_CLASS_BRIDGE_PCMCIA: return "PCMCIA bridge";
306 case PCI_CLASS_BRIDGE_NUBUS: return "NuBus bridge";
307 case PCI_CLASS_BRIDGE_CARDBUS: return "CardBus bridge";
308 case PCI_CLASS_BRIDGE_OTHER: return "Bridge";
309
310 case PCI_CLASS_COMMUNICATION_SERIAL: return "Serial controller";
311 case PCI_CLASS_COMMUNICATION_PARALLEL: return "Parallel controller";
312 case PCI_CLASS_COMMUNICATION_OTHER: return "Communication controller";
313
314 case PCI_CLASS_SYSTEM_PIC: return "PIC";
315 case PCI_CLASS_SYSTEM_DMA: return "DMA controller";
316 case PCI_CLASS_SYSTEM_TIMER: return "Timer";
317 case PCI_CLASS_SYSTEM_RTC: return "RTC";
318 case PCI_CLASS_SYSTEM_OTHER: return "System peripheral";
319
320 case PCI_CLASS_INPUT_KEYBOARD: return "Keyboard controller";
321 case PCI_CLASS_INPUT_PEN: return "Digitizer Pen";
322 case PCI_CLASS_INPUT_MOUSE: return "Mouse controller";
323 case PCI_CLASS_INPUT_OTHER: return "Input device controller";
324
325 case PCI_CLASS_DOCKING_GENERIC: return "Generic Docking Station";
326 case PCI_CLASS_DOCKING_OTHER: return "Docking Station";
327
328 case PCI_CLASS_PROCESSOR_386: return "386";
329 case PCI_CLASS_PROCESSOR_486: return "486";
330 case PCI_CLASS_PROCESSOR_PENTIUM: return "Pentium";
331 case PCI_CLASS_PROCESSOR_ALPHA: return "Alpha";
332 case PCI_CLASS_PROCESSOR_POWERPC: return "Power PC";
333 case PCI_CLASS_PROCESSOR_CO: return "Co-processor";
334
335 case PCI_CLASS_SERIAL_FIREWIRE: return "FireWire (IEEE 1394)";
336 case PCI_CLASS_SERIAL_ACCESS: return "ACCESS Bus";
337 case PCI_CLASS_SERIAL_SSA: return "SSA";
338 case PCI_CLASS_SERIAL_FIBER: return "Fiber Channel";
339
340 default: return "Unknown class";
341 }
342 }
343
344
345 const char *pci_strvendor(unsigned int vendor)
346 {
347 switch (vendor) {
348 case PCI_VENDOR_ID_NCR: return "NCR";
349 case PCI_VENDOR_ID_ADAPTEC: return "Adaptec";
350 case PCI_VENDOR_ID_DPT: return "DPT";
351 case PCI_VENDOR_ID_S3: return "S3 Inc.";
352 case PCI_VENDOR_ID_OPTI: return "OPTI";
353 case PCI_VENDOR_ID_UMC: return "UMC";
354 case PCI_VENDOR_ID_DEC: return "DEC";
355 case PCI_VENDOR_ID_MATROX: return "Matrox";
356 case PCI_VENDOR_ID_INTEL: return "Intel";
357 #if 0
358 case PCI_VENDOR_ID_SMC: return "SMC";
359 #else
360 case PCI_VENDOR_ID_PCTECH: return "PCTECH";
361 #endif
362 case PCI_VENDOR_ID_ATI: return "ATI";
363 case PCI_VENDOR_ID_WEITEK: return "Weitek";
364 case PCI_VENDOR_ID_CIRRUS: return "Cirrus Logic";
365 case PCI_VENDOR_ID_BUSLOGIC: return "Bus Logic";
366 case PCI_VENDOR_ID_N9: return "Number Nine";
367 case PCI_VENDOR_ID_AI: return "Acer Incorporated";
368 case PCI_VENDOR_ID_AL: return "Acer Labs";
369 case PCI_VENDOR_ID_TSENG: return "Tseng'Lab";
370 case PCI_VENDOR_ID_CMD: return "CMD";
371 case PCI_VENDOR_ID_VISION: return "Vision";
372 case PCI_VENDOR_ID_AMD: return "AMD";
373 case PCI_VENDOR_ID_VLSI: return "VLSI";
374 case PCI_VENDOR_ID_ADL: return "Advance Logic";
375 case PCI_VENDOR_ID_SYMPHONY: return "Symphony";
376 case PCI_VENDOR_ID_TRIDENT: return "Trident";
377 case PCI_VENDOR_ID_CONTAQ: return "Contaq";
378 case PCI_VENDOR_ID_NS: return "NS";
379 case PCI_VENDOR_ID_VIA: return "VIA Technologies";
380 case PCI_VENDOR_ID_SI: return "Silicon Integrated Systems";
381 case PCI_VENDOR_ID_LEADTEK: return "Leadtek Research";
382 case PCI_VENDOR_ID_IMS: return "IMS";
383 case PCI_VENDOR_ID_ZEINET: return "ZeiNet";
384 case PCI_VENDOR_ID_EF: return "Efficient Networks";
385 case PCI_VENDOR_ID_HER: return "Hercules";
386 case PCI_VENDOR_ID_ATRONICS: return "Atronics";
387 case PCI_VENDOR_ID_CT: return "Chips & Technologies";
388 case PCI_VENDOR_ID_FD: return "Future Domain";
389 case PCI_VENDOR_ID_WINBOND: return "Winbond";
390 case PCI_VENDOR_ID_3COM: return "3Com";
391 case PCI_VENDOR_ID_PROMISE: return "Promise Technology";
392 case PCI_VENDOR_ID_QLOGIC: return "Q Logic";
393 case PCI_VENDOR_ID_X: return "X TECHNOLOGY";
394 case PCI_VENDOR_ID_ACC: return "ACC MICROELECTRONICS";
395 case PCI_VENDOR_ID_VORTEX: return "VORTEX";
396 case PCI_VENDOR_ID_HP: return "Hewlett Packard";
397 case PCI_VENDOR_ID_IMAGINGTECH: return "Imaging Technology";
398 case PCI_VENDOR_ID_CYCLADES: return "Cyclades";
399 case PCI_VENDOR_ID_OLICOM: return "Olicom";
400 default: return "Unknown vendor";
401 }
402 }
403
404
405 const char *pci_strdev(unsigned int vendor, unsigned int device)
406 {
407 struct pci_dev_info *info;
408
409 info = pci_lookup_dev(vendor, device);
410 return info ? info->name : "Unknown device";
411 }
412
413
414
415
416
417
418 static void burst_bridge(unsigned char bus, unsigned char devfn,
419 unsigned char pos, int turn_on)
420 {
421 #ifdef CONFIG_PCI_OPTIMIZE
422 struct bridge_mapping_type *bmap;
423 unsigned char val;
424 int i;
425
426 pos *= NUM_OPTIMIZATIONS;
427 printk("PCI bridge optimization.\n");
428 for (i = 0; i < NUM_OPTIMIZATIONS; i++) {
429 printk(" %s: ", bridge_optimization[i].type);
430 bmap = &bridge_mapping[pos + i];
431 if (!bmap->addr) {
432 printk("Not supported.");
433 } else {
434 pcibios_read_config_byte(bus, devfn, bmap->addr, &val);
435 if ((val & bmap->mask) == bmap->value) {
436 printk("%s.", bridge_optimization[i].on);
437 if (!turn_on) {
438 pcibios_write_config_byte(bus, devfn,
439 bmap->addr,
440 (val | bmap->mask)
441 - bmap->value);
442 printk("Changed! Now %s.", bridge_optimization[i].off);
443 }
444 } else {
445 printk("%s.", bridge_optimization[i].off);
446 if (turn_on) {
447 pcibios_write_config_byte(bus, devfn,
448 bmap->addr,
449 (val & (0xff - bmap->mask))
450 + bmap->value);
451 printk("Changed! Now %s.", bridge_optimization[i].on);
452 }
453 }
454 }
455 printk("\n");
456 }
457 #endif
458 }
459
460
461
462
463
464
465
466
467 static int sprint_dev_config(struct pci_dev *dev, char *buf, int size)
468 {
469 unsigned long base;
470 unsigned int l, class_rev, bus, devfn;
471 unsigned short vendor, device, status;
472 unsigned char bist, latency, min_gnt, max_lat;
473 int reg, len = 0;
474 const char *str;
475
476 bus = dev->bus->number;
477 devfn = dev->devfn;
478
479 pcibios_read_config_dword(bus, devfn, PCI_CLASS_REVISION, &class_rev);
480 pcibios_read_config_word (bus, devfn, PCI_VENDOR_ID, &vendor);
481 pcibios_read_config_word (bus, devfn, PCI_DEVICE_ID, &device);
482 pcibios_read_config_word (bus, devfn, PCI_STATUS, &status);
483 pcibios_read_config_byte (bus, devfn, PCI_BIST, &bist);
484 pcibios_read_config_byte (bus, devfn, PCI_LATENCY_TIMER, &latency);
485 pcibios_read_config_byte (bus, devfn, PCI_MIN_GNT, &min_gnt);
486 pcibios_read_config_byte (bus, devfn, PCI_MAX_LAT, &max_lat);
487 if (len + 80 > size) {
488 return -1;
489 }
490 len += sprintf(buf + len, " Bus %2d, device %3d, function %2d:\n",
491 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
492
493 if (len + 80 > size) {
494 return -1;
495 }
496 len += sprintf(buf + len, " %s: %s %s (rev %d).\n ",
497 pci_strclass(class_rev >> 8), pci_strvendor(vendor),
498 pci_strdev(vendor, device), class_rev & 0xff);
499
500 if (!pci_lookup_dev(vendor, device)) {
501 len += sprintf(buf + len,
502 "Vendor id=%x. Device id=%x.\n ",
503 vendor, device);
504 }
505
506 str = 0;
507 switch (status & PCI_STATUS_DEVSEL_MASK) {
508 case PCI_STATUS_DEVSEL_FAST: str = "Fast devsel. "; break;
509 case PCI_STATUS_DEVSEL_MEDIUM: str = "Medium devsel. "; break;
510 case PCI_STATUS_DEVSEL_SLOW: str = "Slow devsel. "; break;
511 }
512 if (len + strlen(str) > size) {
513 return -1;
514 }
515 len += sprintf(buf + len, str);
516
517 if (status & PCI_STATUS_FAST_BACK) {
518 # define fast_b2b_capable "Fast back-to-back capable. "
519 if (len + strlen(fast_b2b_capable) > size) {
520 return -1;
521 }
522 len += sprintf(buf + len, fast_b2b_capable);
523 # undef fast_b2b_capable
524 }
525
526 if (bist & PCI_BIST_CAPABLE) {
527 # define BIST_capable "BIST capable. "
528 if (len + strlen(BIST_capable) > size) {
529 return -1;
530 }
531 len += sprintf(buf + len, BIST_capable);
532 # undef BIST_capable
533 }
534
535 if (dev->irq) {
536 if (len + 40 > size) {
537 return -1;
538 }
539 len += sprintf(buf + len, "IRQ %d. ", dev->irq);
540 }
541
542 if (dev->master) {
543 if (len + 80 > size) {
544 return -1;
545 }
546 len += sprintf(buf + len, "Master Capable. ");
547 if (latency)
548 len += sprintf(buf + len, "Latency=%d. ", latency);
549 else
550 len += sprintf(buf + len, "No bursts. ");
551 if (min_gnt)
552 len += sprintf(buf + len, "Min Gnt=%d.", min_gnt);
553 if (max_lat)
554 len += sprintf(buf + len, "Max Lat=%d.", max_lat);
555 }
556
557 for (reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4) {
558 if (len + 40 > size) {
559 return -1;
560 }
561 pcibios_read_config_dword(bus, devfn, reg, &l);
562 base = l;
563 if (!base) {
564 continue;
565 }
566
567 if (base & PCI_BASE_ADDRESS_SPACE_IO) {
568 len += sprintf(buf + len,
569 "\n I/O at 0x%lx.",
570 base & PCI_BASE_ADDRESS_IO_MASK);
571 } else {
572 const char *pref, *type = "unknown";
573
574 if (base & PCI_BASE_ADDRESS_MEM_PREFETCH) {
575 pref = "P";
576 } else {
577 pref = "Non-p";
578 }
579 switch (base & PCI_BASE_ADDRESS_MEM_TYPE_MASK) {
580 case PCI_BASE_ADDRESS_MEM_TYPE_32:
581 type = "32 bit"; break;
582 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
583 type = "20 bit"; break;
584 case PCI_BASE_ADDRESS_MEM_TYPE_64:
585 type = "64 bit";
586
587 reg += 4;
588 pcibios_read_config_dword(bus, devfn, reg, &l);
589 base |= ((u64) l) << 32;
590 break;
591 }
592 len += sprintf(buf + len,
593 "\n %srefetchable %s memory at "
594 "0x%lx.", pref, type,
595 base & PCI_BASE_ADDRESS_MEM_MASK);
596 }
597 }
598
599 len += sprintf(buf + len, "\n");
600 return len;
601 }
602
603
604
605
606
607
608 int get_pci_list(char *buf)
609 {
610 int nprinted, len, size;
611 struct pci_dev *dev;
612 # define MSG "\nwarning: page-size limit reached!\n"
613
614
615 size = PAGE_SIZE - (strlen(MSG) + 1);
616 len = sprintf(buf, "PCI devices found:\n");
617
618 for (dev = pci_devices; dev; dev = dev->next) {
619 nprinted = sprint_dev_config(dev, buf + len, size - len);
620 if (nprinted < 0) {
621 return len + sprintf(buf + len, MSG);
622 }
623 len += nprinted;
624 }
625 return len;
626 }
627
628
629
630
631
632
633 static void *pci_malloc(long size, unsigned long *mem_startp)
634 {
635 void *mem;
636
637 #ifdef DEBUG
638 printk("...pci_malloc(size=%ld,mem=%p)", size, *mem_startp);
639 #endif
640 mem = (void*) *mem_startp;
641 *mem_startp += (size + sizeof(void*) - 1) & ~(sizeof(void*) - 1);
642 memset(mem, 0, size);
643 return mem;
644 }
645
646
647 static unsigned int scan_bus(struct pci_bus *bus, unsigned long *mem_startp)
648 {
649 unsigned int devfn, l, max;
650 unsigned char cmd, tmp, hdr_type = 0;
651 struct pci_dev_info *info;
652 struct pci_dev *dev;
653 struct pci_bus *child;
654
655 #ifdef DEBUG
656 printk("...scan_bus(busno=%d,mem=%p)\n", bus->number, *mem_startp);
657 #endif
658
659 max = bus->secondary;
660 for (devfn = 0; devfn < 0xff; ++devfn) {
661 if (PCI_FUNC(devfn) == 0) {
662 pcibios_read_config_byte(bus->number, devfn,
663 PCI_HEADER_TYPE, &hdr_type);
664 } else if (!(hdr_type & 0x80)) {
665
666 continue;
667 }
668
669 pcibios_read_config_dword(bus->number, devfn, PCI_VENDOR_ID,
670 &l);
671
672 if (l == 0xffffffff || l == 0x00000000) {
673 hdr_type = 0;
674 continue;
675 }
676
677 dev = pci_malloc(sizeof(*dev), mem_startp);
678 dev->bus = bus;
679
680
681
682
683
684 dev->next = pci_devices;
685 pci_devices = dev;
686
687 dev->devfn = devfn;
688 dev->vendor = l & 0xffff;
689 dev->device = (l >> 16) & 0xffff;
690
691
692
693
694
695
696 info = pci_lookup_dev(dev->vendor, dev->device);
697 if (!info) {
698 printk("Warning : Unknown PCI device. Please read include/linux/pci.h \n");
699 } else {
700
701 if (info->bridge_type != 0xff) {
702 burst_bridge(bus->number, devfn,
703 info->bridge_type, 1);
704 }
705 }
706
707
708 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
709 &cmd);
710 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
711 cmd | PCI_COMMAND_MASTER);
712 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
713 &tmp);
714 dev->master = ((tmp & PCI_COMMAND_MASTER) != 0);
715 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
716 cmd);
717
718
719 pcibios_read_config_byte(bus->number, devfn,
720 PCI_INTERRUPT_LINE, &dev->irq);
721
722
723 pcibios_read_config_dword(bus->number, devfn,
724 PCI_CLASS_REVISION, &l);
725 l = l >> 8;
726 dev->class = l;
727
728
729
730
731 dev->sibling = bus->devices;
732 bus->devices = dev;
733
734 if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI) {
735 unsigned int buses;
736 unsigned short cr;
737
738
739
740
741 child = pci_malloc(sizeof(*child), mem_startp);
742 child->next = bus->children;
743 bus->children = child;
744 child->self = dev;
745 child->parent = bus;
746
747
748
749
750
751 child->number = child->secondary = ++max;
752 child->primary = bus->secondary;
753 child->subordinate = 0xff;
754
755
756
757
758 pcibios_read_config_word(bus->number, devfn,
759 PCI_COMMAND, &cr);
760 pcibios_write_config_word(bus->number, devfn,
761 PCI_COMMAND, 0x0000);
762 pcibios_write_config_word(bus->number, devfn,
763 PCI_STATUS, 0xffff);
764
765
766
767 pcibios_read_config_dword(bus->number, devfn, 0x18,
768 &buses);
769 buses &= 0xff000000;
770 buses |= (((unsigned int)(child->primary) << 0) |
771 ((unsigned int)(child->secondary) << 8) |
772 ((unsigned int)(child->subordinate) << 16));
773 pcibios_write_config_dword(bus->number, devfn, 0x18,
774 buses);
775
776
777
778 max = scan_bus(child, mem_startp);
779
780
781
782
783 child->subordinate = max;
784 buses = (buses & 0xff00ffff)
785 | ((unsigned int)(child->subordinate) << 16);
786 pcibios_write_config_dword(bus->number, devfn, 0x18,
787 buses);
788 pcibios_write_config_word(bus->number, devfn,
789 PCI_COMMAND, cr);
790 }
791 }
792
793
794
795
796
797
798
799 return max;
800 }
801
802
803 unsigned long pci_init (unsigned long mem_start, unsigned long mem_end)
804 {
805 mem_start = pcibios_init(mem_start, mem_end);
806
807 if (!pcibios_present()) {
808 printk("pci_init: no BIOS32 detected\n");
809 return mem_start;
810 }
811
812 printk("Probing PCI hardware.\n");
813
814 memset(&pci_root, 0, sizeof(pci_root));
815 pci_root.subordinate = scan_bus(&pci_root, &mem_start);
816
817
818 mem_start = pcibios_fixup(mem_start, mem_end);
819
820 #ifdef DEBUG
821 {
822 int len = get_pci_list((char*)mem_start);
823 if (len) {
824 ((char *) mem_start)[len] = '\0';
825 printk("%s\n", (char *) mem_start);
826 }
827 }
828 #endif
829 return mem_start;
830 }
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