This source file includes following definitions.
- pci_lookup_dev
- pci_strclass
- pci_strvendor
- pci_strdev
- burst_bridge
- sprint_dev_config
- get_pci_list
- pci_malloc
- scan_bus
- pci_init
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8
9 #include <linux/config.h>
10 #include <linux/ptrace.h>
11 #include <linux/types.h>
12 #include <linux/kernel.h>
13 #include <linux/bios32.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16
17 #include <asm/page.h>
18
19 struct pci_bus pci_root;
20 struct pci_dev *pci_devices = 0;
21
22
23
24
25
26
27
28
29
30
31
32 #define DEVICE(vid,did,name) \
33 {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), 0xff}
34
35 #define BRIDGE(vid,did,name,bridge) \
36 {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), (bridge)}
37
38
39
40
41
42
43 struct pci_dev_info dev_info[] = {
44 DEVICE( COMPAQ, COMPAQ_1280, "QVision 1280/p"),
45 DEVICE( NCR, NCR_53C810, "53c810"),
46 DEVICE( NCR, NCR_53C820, "53c820"),
47 DEVICE( NCR, NCR_53C825, "53c825"),
48 DEVICE( NCR, NCR_53C815, "53c815"),
49 DEVICE( ATI, ATI_68800, "68800AX"),
50 DEVICE( ATI, ATI_215CT222, "215CT222"),
51 DEVICE( ATI, ATI_210888CX, "210888CX"),
52 DEVICE( ATI, ATI_210888GX, "210888GX"),
53 DEVICE( VLSI, VLSI_82C592, "82C592-FC1"),
54 DEVICE( VLSI, VLSI_82C593, "82C593-FC1"),
55 DEVICE( ADL, ADL_2301, "2301"),
56 DEVICE( NS, NS_87410, "87410"),
57 DEVICE( TSENG, TSENG_W32P_2, "ET4000W32P"),
58 DEVICE( TSENG, TSENG_W32P_b, "ET4000W32P rev B"),
59 DEVICE( TSENG, TSENG_W32P_c, "ET4000W32P rev C"),
60 DEVICE( TSENG, TSENG_W32P_d, "ET4000W32P rev D"),
61 DEVICE( WEITEK, WEITEK_P9000, "P9000"),
62 DEVICE( WEITEK, WEITEK_P9100, "P9100"),
63 BRIDGE( DEC, DEC_BRD, "DC21050", 0x00),
64 DEVICE( DEC, DEC_TULIP, "DC21040"),
65 DEVICE( DEC, DEC_TGA, "DC21030"),
66 DEVICE( DEC, DEC_TULIP_FAST, "DC21140"),
67 DEVICE( DEC, DEC_FDDI, "DEFPA"),
68 DEVICE( DEC, DEC_TULIP_PLUS, "DC21041"),
69 DEVICE( CIRRUS, CIRRUS_5430, "GD 5430"),
70 DEVICE( CIRRUS, CIRRUS_5434_4, "GD 5434"),
71 DEVICE( CIRRUS, CIRRUS_5434_8, "GD 5434"),
72 DEVICE( CIRRUS, CIRRUS_6729, "CL 6729"),
73 DEVICE( CIRRUS, CIRRUS_7542, "CL 7542"),
74 DEVICE( AMD, AMD_LANCE, "79C970"),
75 DEVICE( AMD, AMD_SCSI, "53C974"),
76 DEVICE( TRIDENT, TRIDENT_9420, "TG 9420"),
77 DEVICE( TRIDENT, TRIDENT_9440, "TG 9440"),
78 DEVICE( TRIDENT, TRIDENT_9660, "TG 9660"),
79 DEVICE( AI, AI_M1435, "M1435"),
80 DEVICE( MATROX, MATROX_MGA_2, "Atlas PX2085"),
81 DEVICE( MATROX, MATROX_MIL ,"Millenium"),
82 DEVICE( MATROX, MATROX_MGA_IMP, "MGA Impression"),
83 DEVICE( CT, CT_65545, "65545"),
84 DEVICE( FD, FD_36C70, "TMC-18C30"),
85 DEVICE( SI, SI_503, "85C503"),
86 DEVICE( SI, SI_501, "85C501"),
87 DEVICE( SI, SI_496, "85C496"),
88 DEVICE( SI, SI_601, "85C601"),
89 DEVICE( SI, SI_5511, "85C5511"),
90 DEVICE( SI, SI_5513, "85C5513"),
91 DEVICE( HP, HP_J2585A, "J2585A"),
92 DEVICE( PCTECH, PCTECH_RZ1000, "RZ1000 (buggy)"),
93 DEVICE( DPT, DPT, "SmartCache/Raid"),
94 DEVICE( OPTI, OPTI_82C557, "82C557"),
95 DEVICE( OPTI, OPTI_82C558, "82C558"),
96 DEVICE( OPTI, OPTI_82C621, "82C621"),
97 DEVICE( OPTI, OPTI_82C822, "82C822"),
98 DEVICE( BUSLOGIC, BUSLOGIC_946C_2,"946C"),
99 DEVICE( BUSLOGIC, BUSLOGIC_946C, "946C"),
100 DEVICE( BUSLOGIC, BUSLOGIC_930, "BT-930"),
101 DEVICE( PROMISE, PROMISE_5300, "DC5030"),
102 DEVICE( N9, N9_I128, "Imagine 128"),
103 DEVICE( UMC, UMC_UM8673F, "UM8673F"),
104 BRIDGE( UMC, UMC_UM8891A, "UM8891A", 0x01),
105 DEVICE( UMC, UMC_UM8886A, "UM8886A"),
106 BRIDGE( UMC, UMC_UM8881F, "UM8881F", 0x02),
107 DEVICE( UMC, UMC_UM8886F, "UM8886F"),
108 DEVICE( UMC, UMC_UM9017F, "UM9017F"),
109 DEVICE( X, X_AGX016, "ITT AGX016"),
110 DEVICE( QLOGIC, QLOGIC_ISP1020, "ISP1020"),
111 DEVICE( QLOGIC, QLOGIC_ISP1022, "ISP1022"),
112 DEVICE( LEADTEK, LEADTEK_805, "S3 805"),
113 DEVICE( CONTAQ, CONTAQ_82C599, "82C599"),
114 DEVICE( CMD, CMD_640, "640 (buggy)"),
115 DEVICE( CMD, CMD_646, "646"),
116 DEVICE( VISION, VISION_QD8500, "QD-8500"),
117 DEVICE( VISION, VISION_QD8580, "QD-8580"),
118 DEVICE( SIERRA, SIERRA_STB, "STB Horizon 64"),
119 DEVICE( WINBOND, WINBOND_83769, "W83769F"),
120 DEVICE( 3COM, 3COM_3C590, "3C590 10bT"),
121 DEVICE( 3COM, 3COM_3C595TX, "3C595 100bTX"),
122 DEVICE( 3COM, 3COM_3C595T4, "3C595 100bT4"),
123 DEVICE( 3COM, 3COM_3C595MII, "3C595 100b-MII"),
124 DEVICE( AL, AL_M1445, "M1445"),
125 DEVICE( AL, AL_M1449, "M1449"),
126 DEVICE( AL, AL_M1451, "M1451"),
127 DEVICE( AL, AL_M1461, "M1461"),
128 DEVICE( AL, AL_M4803, "M4803"),
129 DEVICE( ASP, ASP_ABP940, "ABP940"),
130 DEVICE( IMS, IMS_8849, "8849"),
131 DEVICE( TEKRAM2, TEKRAM2_690c, "DC690c"),
132 DEVICE( REALTEK, REALTEK_8029, "8029"),
133 DEVICE( VIA, VIA_82C505, "VT 82C505"),
134 DEVICE( VIA, VIA_82C561, "VT 82C561"),
135 DEVICE( VIA, VIA_82C576, "VT 82C576 3V"),
136 DEVICE( VORTEX, VORTEX_GDT, "GDT 6000b"),
137 DEVICE( EF, EF_ATM_FPGA, "155P-MF1 (FPGA)"),
138 DEVICE( EF, EF_ATM_ASIC, "155P-MF1 (ASIC)"),
139 DEVICE( IMAGINGTECH, IMAGINGTECH_ICPCI, "MVC IC-PCI"),
140 DEVICE( PLX, PLX_9060, "PCI9060 i960 bridge"),
141 DEVICE( ALLIANCE, ALLIANCE_PROVIDEO, "Provideo"),
142 DEVICE( MUTECH, MUTECH_MV1000, "MV-1000"),
143 DEVICE( ZEITNET, ZEITNET_1221, "1221"),
144 DEVICE( HAL, HAL_RIO, "RIO host"),
145 DEVICE( CYCLADES, CYCLADES_Y, "Cyclome-Y"),
146 DEVICE( SYMPHONY, SYMPHONY_101, "82C101"),
147 DEVICE( TEKRAM, TEKRAM_DC290, "DC-290"),
148 DEVICE( AVANCE, AVANCE_2302, "ALG-2302"),
149 DEVICE( S3, S3_811, "Trio32/Trio64"),
150 DEVICE( S3, S3_868, "Vision 868"),
151 DEVICE( S3, S3_928, "Vision 928-P"),
152 DEVICE( S3, S3_864_1, "Vision 864-P"),
153 DEVICE( S3, S3_864_2, "Vision 864-P"),
154 DEVICE( S3, S3_964_1, "Vision 964-P"),
155 DEVICE( S3, S3_964_2, "Vision 964-P"),
156 DEVICE( S3, S3_968, "Vision 968"),
157 DEVICE( INTEL, INTEL_82375, "82375EB"),
158 BRIDGE( INTEL, INTEL_82424, "82424ZX Saturn", 0x00),
159 DEVICE( INTEL, INTEL_82378, "82378IB"),
160 DEVICE( INTEL, INTEL_82430, "82430ZX Aries"),
161 BRIDGE( INTEL, INTEL_82434, "82434LX Mercury/Neptune", 0x00),
162 DEVICE( INTEL, INTEL_7116, "SAA7116"),
163 DEVICE( INTEL, INTEL_82596, "82596"),
164 DEVICE( INTEL, INTEL_82865, "82865"),
165 DEVICE( INTEL, INTEL_82557, "82557"),
166 DEVICE( INTEL, INTEL_82437, "82437"),
167 DEVICE( INTEL, INTEL_82371_0, "82371 Triton PIIX"),
168 DEVICE( INTEL, INTEL_82371_1, "82371 Triton PIIX"),
169 DEVICE( INTEL, INTEL_P6, "Orion P6"),
170 DEVICE( ADAPTEC, ADAPTEC_7850, "AIC-7850"),
171 DEVICE( ADAPTEC, ADAPTEC_7870, "AIC-7870"),
172 DEVICE( ADAPTEC, ADAPTEC_7871, "AIC-7871"),
173 DEVICE( ADAPTEC, ADAPTEC_7872, "AIC-7872"),
174 DEVICE( ADAPTEC, ADAPTEC_7873, "AIC-7873"),
175 DEVICE( ADAPTEC, ADAPTEC_7880, "AIC-7880U"),
176 DEVICE( ADAPTEC, ADAPTEC_7881, "AIC-7881U"),
177 DEVICE( ADAPTEC, ADAPTEC_7882, "AIC-7882U"),
178 DEVICE( ATRONICS, ATRONICS_2015, "IDE-2015PL"),
179 DEVICE( HER, HER_STING, "Stingray"),
180 DEVICE( HER, HER_STINGARK, "Stingray ARK 2000PV")
181 };
182
183
184 #ifdef CONFIG_PCI_OPTIMIZE
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201 struct optimization_type {
202 const char *type;
203 const char *off;
204 const char *on;
205 } bridge_optimization[] = {
206 {"Cache L2", "write trough", "write back"},
207 {"CPU-PCI posted write", "off", "on"},
208 {"CPU-Memory posted write", "off", "on"},
209 {"PCI-Memory posted write", "off", "on"},
210 {"PCI burst", "off", "on"}
211 };
212
213 #define NUM_OPTIMIZATIONS \
214 (sizeof(bridge_optimization) / sizeof(bridge_optimization[0]))
215
216 struct bridge_mapping_type {
217 unsigned char addr;
218 unsigned char mask;
219 unsigned char value;
220 } bridge_mapping[] = {
221
222
223
224
225
226
227
228 {0x0 ,0x02 ,0x02 },
229 {0x53 ,0x02 ,0x02 },
230 {0x53 ,0x01 ,0x01 },
231 {0x54 ,0x01 ,0x01 },
232 {0x54 ,0x02 ,0x02 },
233
234
235
236
237
238 {0x50 ,0x10 ,0x00 },
239 {0x51 ,0x40 ,0x40 },
240 {0x0 ,0x0 ,0x0 },
241 {0x0 ,0x0 ,0x0 },
242 {0x0 ,0x0 ,0x0 },
243
244
245
246
247
248
249 {0x0 ,0x1 ,0x1 },
250 {0x0 ,0x2 ,0x0 },
251 {0x0 ,0x0 ,0x0 },
252 {0x0 ,0x0 ,0x0 },
253 {0x0 ,0x0 ,0x0 }
254 };
255
256 #endif
257
258
259
260
261
262 struct pci_dev_info *pci_lookup_dev(unsigned int vendor, unsigned int dev)
263 {
264 int min = 0,
265 max = sizeof(dev_info)/sizeof(dev_info[0]) - 1;
266
267 for ( ; ; )
268 {
269 int i = (min + max) >> 1;
270 long order;
271
272 order = dev_info[i].vendor - (long) vendor;
273 if (!order)
274 order = dev_info[i].device - (long) dev;
275
276 if (order < 0)
277 {
278 min = i + 1;
279 if ( min > max )
280 return 0;
281 continue;
282 }
283
284 if (order > 0)
285 {
286 max = i - 1;
287 if ( min > max )
288 return 0;
289 continue;
290 }
291
292 return & dev_info[ i ];
293 }
294 }
295
296 const char *pci_strclass (unsigned int class)
297 {
298 switch (class >> 8) {
299 case PCI_CLASS_NOT_DEFINED: return "Non-VGA device";
300 case PCI_CLASS_NOT_DEFINED_VGA: return "VGA compatible device";
301
302 case PCI_CLASS_STORAGE_SCSI: return "SCSI storage controller";
303 case PCI_CLASS_STORAGE_IDE: return "IDE interface";
304 case PCI_CLASS_STORAGE_FLOPPY: return "Floppy disk controller";
305 case PCI_CLASS_STORAGE_IPI: return "IPI bus controller";
306 case PCI_CLASS_STORAGE_RAID: return "RAID bus controller";
307 case PCI_CLASS_STORAGE_OTHER: return "Unknown mass storage controller";
308
309 case PCI_CLASS_NETWORK_ETHERNET: return "Ethernet controller";
310 case PCI_CLASS_NETWORK_TOKEN_RING: return "Token ring network controller";
311 case PCI_CLASS_NETWORK_FDDI: return "FDDI network controller";
312 case PCI_CLASS_NETWORK_ATM: return "ATM network controller";
313 case PCI_CLASS_NETWORK_OTHER: return "Network controller";
314
315 case PCI_CLASS_DISPLAY_VGA: return "VGA compatible controller";
316 case PCI_CLASS_DISPLAY_XGA: return "XGA compatible controller";
317 case PCI_CLASS_DISPLAY_OTHER: return "Display controller";
318
319 case PCI_CLASS_MULTIMEDIA_VIDEO: return "Multimedia video controller";
320 case PCI_CLASS_MULTIMEDIA_AUDIO: return "Multimedia audio controller";
321 case PCI_CLASS_MULTIMEDIA_OTHER: return "Multimedia controller";
322
323 case PCI_CLASS_MEMORY_RAM: return "RAM memory";
324 case PCI_CLASS_MEMORY_FLASH: return "FLASH memory";
325 case PCI_CLASS_MEMORY_OTHER: return "Memory";
326
327 case PCI_CLASS_BRIDGE_HOST: return "Host bridge";
328 case PCI_CLASS_BRIDGE_ISA: return "ISA bridge";
329 case PCI_CLASS_BRIDGE_EISA: return "EISA bridge";
330 case PCI_CLASS_BRIDGE_MC: return "MicroChannel bridge";
331 case PCI_CLASS_BRIDGE_PCI: return "PCI bridge";
332 case PCI_CLASS_BRIDGE_PCMCIA: return "PCMCIA bridge";
333 case PCI_CLASS_BRIDGE_NUBUS: return "NuBus bridge";
334 case PCI_CLASS_BRIDGE_CARDBUS: return "CardBus bridge";
335 case PCI_CLASS_BRIDGE_OTHER: return "Bridge";
336
337 case PCI_CLASS_COMMUNICATION_SERIAL: return "Serial controller";
338 case PCI_CLASS_COMMUNICATION_PARALLEL: return "Parallel controller";
339 case PCI_CLASS_COMMUNICATION_OTHER: return "Communication controller";
340
341 case PCI_CLASS_SYSTEM_PIC: return "PIC";
342 case PCI_CLASS_SYSTEM_DMA: return "DMA controller";
343 case PCI_CLASS_SYSTEM_TIMER: return "Timer";
344 case PCI_CLASS_SYSTEM_RTC: return "RTC";
345 case PCI_CLASS_SYSTEM_OTHER: return "System peripheral";
346
347 case PCI_CLASS_INPUT_KEYBOARD: return "Keyboard controller";
348 case PCI_CLASS_INPUT_PEN: return "Digitizer Pen";
349 case PCI_CLASS_INPUT_MOUSE: return "Mouse controller";
350 case PCI_CLASS_INPUT_OTHER: return "Input device controller";
351
352 case PCI_CLASS_DOCKING_GENERIC: return "Generic Docking Station";
353 case PCI_CLASS_DOCKING_OTHER: return "Docking Station";
354
355 case PCI_CLASS_PROCESSOR_386: return "386";
356 case PCI_CLASS_PROCESSOR_486: return "486";
357 case PCI_CLASS_PROCESSOR_PENTIUM: return "Pentium";
358 case PCI_CLASS_PROCESSOR_ALPHA: return "Alpha";
359 case PCI_CLASS_PROCESSOR_POWERPC: return "Power PC";
360 case PCI_CLASS_PROCESSOR_CO: return "Co-processor";
361
362 case PCI_CLASS_SERIAL_FIREWIRE: return "FireWire (IEEE 1394)";
363 case PCI_CLASS_SERIAL_ACCESS: return "ACCESS Bus";
364 case PCI_CLASS_SERIAL_SSA: return "SSA";
365 case PCI_CLASS_SERIAL_FIBER: return "Fiber Channel";
366
367 default: return "Unknown class";
368 }
369 }
370
371
372 const char *pci_strvendor(unsigned int vendor)
373 {
374 switch (vendor) {
375 case PCI_VENDOR_ID_COMPAQ: return "Compaq";
376 case PCI_VENDOR_ID_NCR: return "NCR";
377 case PCI_VENDOR_ID_ATI: return "ATI";
378 case PCI_VENDOR_ID_VLSI: return "VLSI";
379 case PCI_VENDOR_ID_ADL: return "Advance Logic";
380 case PCI_VENDOR_ID_NS: return "NS";
381 case PCI_VENDOR_ID_TSENG: return "Tseng'Lab";
382 case PCI_VENDOR_ID_WEITEK: return "Weitek";
383 case PCI_VENDOR_ID_DEC: return "DEC";
384 case PCI_VENDOR_ID_CIRRUS: return "Cirrus Logic";
385 case PCI_VENDOR_ID_IBM: return "IBM";
386 case PCI_VENDOR_ID_AMD: return "AMD";
387 case PCI_VENDOR_ID_TRIDENT: return "Trident";
388 case PCI_VENDOR_ID_AI: return "Acer Incorporated";
389 case PCI_VENDOR_ID_MATROX: return "Matrox";
390 case PCI_VENDOR_ID_CT: return "Chips & Technologies";
391 case PCI_VENDOR_ID_FD: return "Future Domain";
392 case PCI_VENDOR_ID_SI: return "Silicon Integrated Systems";
393 case PCI_VENDOR_ID_HP: return "Hewlett Packard";
394 case PCI_VENDOR_ID_PCTECH: return "PCTECH";
395 case PCI_VENDOR_ID_DPT: return "DPT";
396 case PCI_VENDOR_ID_OPTI: return "OPTI";
397 case PCI_VENDOR_ID_BUSLOGIC: return "BusLogic";
398 case PCI_VENDOR_ID_PROMISE: return "Promise Technology";
399 case PCI_VENDOR_ID_N9: return "Number Nine";
400 case PCI_VENDOR_ID_UMC: return "UMC";
401 case PCI_VENDOR_ID_X: return "X TECHNOLOGY";
402 case PCI_VENDOR_ID_QLOGIC: return "Q Logic";
403 case PCI_VENDOR_ID_LEADTEK: return "Leadtek Research";
404 case PCI_VENDOR_ID_CONTAQ: return "Contaq";
405 case PCI_VENDOR_ID_OLICOM: return "Olicom";
406 case PCI_VENDOR_ID_CMD: return "CMD";
407 case PCI_VENDOR_ID_VISION: return "Vision";
408 case PCI_VENDOR_ID_SIERRA: return "Sierra";
409 case PCI_VENDOR_ID_ACC: return "ACC MICROELECTRONICS";
410 case PCI_VENDOR_ID_WINBOND: return "Winbond";
411 case PCI_VENDOR_ID_3COM: return "3Com";
412 case PCI_VENDOR_ID_AL: return "Acer Labs";
413 case PCI_VENDOR_ID_ASP: return "Advanced System Products";
414 case PCI_VENDOR_ID_IMS: return "IMS";
415 case PCI_VENDOR_ID_TEKRAM2: return "Tekram";
416 case PCI_VENDOR_ID_REALTEK: return "Realtek";
417 case PCI_VENDOR_ID_VIA: return "VIA Technologies";
418 case PCI_VENDOR_ID_VORTEX: return "VORTEX";
419 case PCI_VENDOR_ID_EF: return "Efficient Networks";
420 case PCI_VENDOR_ID_IMAGINGTECH: return "Imaging Technology";
421 case PCI_VENDOR_ID_PLX: return "PLX";
422 case PCI_VENDOR_ID_ALLIANCE: return "Alliance";
423 case PCI_VENDOR_ID_MUTECH: return "Mutech";
424 case PCI_VENDOR_ID_ZEITNET: return "ZeitNet";
425 case PCI_VENDOR_ID_HAL: return "HAL";
426 case PCI_VENDOR_ID_CYCLADES: return "Cyclades";
427 case PCI_VENDOR_ID_SYMPHONY: return "Symphony";
428 case PCI_VENDOR_ID_TEKRAM: return "Tekram";
429 case PCI_VENDOR_ID_AVANCE: return "Avance";
430 case PCI_VENDOR_ID_S3: return "S3 Inc.";
431 case PCI_VENDOR_ID_INTEL: return "Intel";
432 case PCI_VENDOR_ID_ADAPTEC: return "Adaptec";
433 case PCI_VENDOR_ID_ATRONICS: return "Atronics";
434 case PCI_VENDOR_ID_HER: return "Hercules";
435 default: return "Unknown vendor";
436 }
437 }
438
439
440 const char *pci_strdev(unsigned int vendor, unsigned int device)
441 {
442 struct pci_dev_info *info;
443
444 info = pci_lookup_dev(vendor, device);
445 return info ? info->name : "Unknown device";
446 }
447
448
449
450
451
452
453 static void burst_bridge(unsigned char bus, unsigned char devfn,
454 unsigned char pos, int turn_on)
455 {
456 #ifdef CONFIG_PCI_OPTIMIZE
457 struct bridge_mapping_type *bmap;
458 unsigned char val;
459 int i;
460
461 pos *= NUM_OPTIMIZATIONS;
462 printk("PCI bridge optimization.\n");
463 for (i = 0; i < NUM_OPTIMIZATIONS; i++) {
464 printk(" %s: ", bridge_optimization[i].type);
465 bmap = &bridge_mapping[pos + i];
466 if (!bmap->addr) {
467 printk("Not supported.");
468 } else {
469 pcibios_read_config_byte(bus, devfn, bmap->addr, &val);
470 if ((val & bmap->mask) == bmap->value) {
471 printk("%s.", bridge_optimization[i].on);
472 if (!turn_on) {
473 pcibios_write_config_byte(bus, devfn,
474 bmap->addr,
475 (val | bmap->mask)
476 - bmap->value);
477 printk("Changed! Now %s.", bridge_optimization[i].off);
478 }
479 } else {
480 printk("%s.", bridge_optimization[i].off);
481 if (turn_on) {
482 pcibios_write_config_byte(bus, devfn,
483 bmap->addr,
484 (val & (0xff - bmap->mask))
485 + bmap->value);
486 printk("Changed! Now %s.", bridge_optimization[i].on);
487 }
488 }
489 }
490 printk("\n");
491 }
492 #endif
493 }
494
495
496
497
498
499
500
501
502 static int sprint_dev_config(struct pci_dev *dev, char *buf, int size)
503 {
504 unsigned long base;
505 unsigned int l, class_rev, bus, devfn;
506 unsigned short vendor, device, status;
507 unsigned char bist, latency, min_gnt, max_lat;
508 int reg, len = 0;
509 const char *str;
510
511 bus = dev->bus->number;
512 devfn = dev->devfn;
513
514 pcibios_read_config_dword(bus, devfn, PCI_CLASS_REVISION, &class_rev);
515 pcibios_read_config_word (bus, devfn, PCI_VENDOR_ID, &vendor);
516 pcibios_read_config_word (bus, devfn, PCI_DEVICE_ID, &device);
517 pcibios_read_config_word (bus, devfn, PCI_STATUS, &status);
518 pcibios_read_config_byte (bus, devfn, PCI_BIST, &bist);
519 pcibios_read_config_byte (bus, devfn, PCI_LATENCY_TIMER, &latency);
520 pcibios_read_config_byte (bus, devfn, PCI_MIN_GNT, &min_gnt);
521 pcibios_read_config_byte (bus, devfn, PCI_MAX_LAT, &max_lat);
522 if (len + 80 > size) {
523 return -1;
524 }
525 len += sprintf(buf + len, " Bus %2d, device %3d, function %2d:\n",
526 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
527
528 if (len + 80 > size) {
529 return -1;
530 }
531 len += sprintf(buf + len, " %s: %s %s (rev %d).\n ",
532 pci_strclass(class_rev >> 8), pci_strvendor(vendor),
533 pci_strdev(vendor, device), class_rev & 0xff);
534
535 if (!pci_lookup_dev(vendor, device)) {
536 len += sprintf(buf + len,
537 "Vendor id=%x. Device id=%x.\n ",
538 vendor, device);
539 }
540
541 str = 0;
542 switch (status & PCI_STATUS_DEVSEL_MASK) {
543 case PCI_STATUS_DEVSEL_FAST: str = "Fast devsel. "; break;
544 case PCI_STATUS_DEVSEL_MEDIUM: str = "Medium devsel. "; break;
545 case PCI_STATUS_DEVSEL_SLOW: str = "Slow devsel. "; break;
546 }
547 if (len + strlen(str) > size) {
548 return -1;
549 }
550 len += sprintf(buf + len, str);
551
552 if (status & PCI_STATUS_FAST_BACK) {
553 # define fast_b2b_capable "Fast back-to-back capable. "
554 if (len + strlen(fast_b2b_capable) > size) {
555 return -1;
556 }
557 len += sprintf(buf + len, fast_b2b_capable);
558 # undef fast_b2b_capable
559 }
560
561 if (bist & PCI_BIST_CAPABLE) {
562 # define BIST_capable "BIST capable. "
563 if (len + strlen(BIST_capable) > size) {
564 return -1;
565 }
566 len += sprintf(buf + len, BIST_capable);
567 # undef BIST_capable
568 }
569
570 if (dev->irq) {
571 if (len + 40 > size) {
572 return -1;
573 }
574 len += sprintf(buf + len, "IRQ %d. ", dev->irq);
575 }
576
577 if (dev->master) {
578 if (len + 80 > size) {
579 return -1;
580 }
581 len += sprintf(buf + len, "Master Capable. ");
582 if (latency)
583 len += sprintf(buf + len, "Latency=%d. ", latency);
584 else
585 len += sprintf(buf + len, "No bursts. ");
586 if (min_gnt)
587 len += sprintf(buf + len, "Min Gnt=%d.", min_gnt);
588 if (max_lat)
589 len += sprintf(buf + len, "Max Lat=%d.", max_lat);
590 }
591
592 for (reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4) {
593 if (len + 40 > size) {
594 return -1;
595 }
596 pcibios_read_config_dword(bus, devfn, reg, &l);
597 base = l;
598 if (!base) {
599 continue;
600 }
601
602 if (base & PCI_BASE_ADDRESS_SPACE_IO) {
603 len += sprintf(buf + len,
604 "\n I/O at 0x%lx.",
605 base & PCI_BASE_ADDRESS_IO_MASK);
606 } else {
607 const char *pref, *type = "unknown";
608
609 if (base & PCI_BASE_ADDRESS_MEM_PREFETCH) {
610 pref = "P";
611 } else {
612 pref = "Non-p";
613 }
614 switch (base & PCI_BASE_ADDRESS_MEM_TYPE_MASK) {
615 case PCI_BASE_ADDRESS_MEM_TYPE_32:
616 type = "32 bit"; break;
617 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
618 type = "20 bit"; break;
619 case PCI_BASE_ADDRESS_MEM_TYPE_64:
620 type = "64 bit";
621
622 reg += 4;
623 pcibios_read_config_dword(bus, devfn, reg, &l);
624 base |= ((u64) l) << 32;
625 break;
626 }
627 len += sprintf(buf + len,
628 "\n %srefetchable %s memory at "
629 "0x%lx.", pref, type,
630 base & PCI_BASE_ADDRESS_MEM_MASK);
631 }
632 }
633
634 len += sprintf(buf + len, "\n");
635 return len;
636 }
637
638
639
640
641
642
643 int get_pci_list(char *buf)
644 {
645 int nprinted, len, size;
646 struct pci_dev *dev;
647 # define MSG "\nwarning: page-size limit reached!\n"
648
649
650 size = PAGE_SIZE - (strlen(MSG) + 1);
651 len = sprintf(buf, "PCI devices found:\n");
652
653 for (dev = pci_devices; dev; dev = dev->next) {
654 nprinted = sprint_dev_config(dev, buf + len, size - len);
655 if (nprinted < 0) {
656 return len + sprintf(buf + len, MSG);
657 }
658 len += nprinted;
659 }
660 return len;
661 }
662
663
664
665
666
667
668 static void *pci_malloc(long size, unsigned long *mem_startp)
669 {
670 void *mem;
671
672 #ifdef DEBUG
673 printk("...pci_malloc(size=%ld,mem=%p)", size, *mem_startp);
674 #endif
675 mem = (void*) *mem_startp;
676 *mem_startp += (size + sizeof(void*) - 1) & ~(sizeof(void*) - 1);
677 memset(mem, 0, size);
678 return mem;
679 }
680
681
682 static unsigned int scan_bus(struct pci_bus *bus, unsigned long *mem_startp)
683 {
684 unsigned int devfn, l, max;
685 unsigned char cmd, tmp, hdr_type = 0;
686 struct pci_dev_info *info;
687 struct pci_dev *dev;
688 struct pci_bus *child;
689
690 #ifdef DEBUG
691 printk("...scan_bus(busno=%d,mem=%p)\n", bus->number, *mem_startp);
692 #endif
693
694 max = bus->secondary;
695 for (devfn = 0; devfn < 0xff; ++devfn) {
696 if (PCI_FUNC(devfn) == 0) {
697 pcibios_read_config_byte(bus->number, devfn,
698 PCI_HEADER_TYPE, &hdr_type);
699 } else if (!(hdr_type & 0x80)) {
700
701 continue;
702 }
703
704 pcibios_read_config_dword(bus->number, devfn, PCI_VENDOR_ID,
705 &l);
706
707 if (l == 0xffffffff || l == 0x00000000) {
708 hdr_type = 0;
709 continue;
710 }
711
712 dev = pci_malloc(sizeof(*dev), mem_startp);
713 dev->bus = bus;
714
715
716
717
718
719 dev->next = pci_devices;
720 pci_devices = dev;
721
722 dev->devfn = devfn;
723 dev->vendor = l & 0xffff;
724 dev->device = (l >> 16) & 0xffff;
725
726
727
728
729
730
731 info = pci_lookup_dev(dev->vendor, dev->device);
732 if (!info) {
733 printk("Warning : Unknown PCI device (%x:%x). Please read include/linux/pci.h \n",
734 dev->vendor, dev->device);
735 } else {
736
737 if (info->bridge_type != 0xff) {
738 burst_bridge(bus->number, devfn,
739 info->bridge_type, 1);
740 }
741 }
742
743
744 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
745 &cmd);
746 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
747 cmd | PCI_COMMAND_MASTER);
748 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
749 &tmp);
750 dev->master = ((tmp & PCI_COMMAND_MASTER) != 0);
751 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
752 cmd);
753
754
755 pcibios_read_config_byte(bus->number, devfn,
756 PCI_INTERRUPT_LINE, &dev->irq);
757
758
759 pcibios_read_config_dword(bus->number, devfn,
760 PCI_CLASS_REVISION, &l);
761 l = l >> 8;
762 dev->class = l;
763
764
765
766
767 dev->sibling = bus->devices;
768 bus->devices = dev;
769
770 if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI) {
771 unsigned int buses;
772 unsigned short cr;
773
774
775
776
777 child = pci_malloc(sizeof(*child), mem_startp);
778 child->next = bus->children;
779 bus->children = child;
780 child->self = dev;
781 child->parent = bus;
782
783
784
785
786
787 child->number = child->secondary = ++max;
788 child->primary = bus->secondary;
789 child->subordinate = 0xff;
790
791
792
793
794 pcibios_read_config_word(bus->number, devfn,
795 PCI_COMMAND, &cr);
796 pcibios_write_config_word(bus->number, devfn,
797 PCI_COMMAND, 0x0000);
798 pcibios_write_config_word(bus->number, devfn,
799 PCI_STATUS, 0xffff);
800
801
802
803 pcibios_read_config_dword(bus->number, devfn, 0x18,
804 &buses);
805 buses &= 0xff000000;
806 buses |= (((unsigned int)(child->primary) << 0) |
807 ((unsigned int)(child->secondary) << 8) |
808 ((unsigned int)(child->subordinate) << 16));
809 pcibios_write_config_dword(bus->number, devfn, 0x18,
810 buses);
811
812
813
814 max = scan_bus(child, mem_startp);
815
816
817
818
819 child->subordinate = max;
820 buses = (buses & 0xff00ffff)
821 | ((unsigned int)(child->subordinate) << 16);
822 pcibios_write_config_dword(bus->number, devfn, 0x18,
823 buses);
824 pcibios_write_config_word(bus->number, devfn,
825 PCI_COMMAND, cr);
826 }
827 }
828
829
830
831
832
833
834
835 return max;
836 }
837
838
839 unsigned long pci_init (unsigned long mem_start, unsigned long mem_end)
840 {
841 mem_start = pcibios_init(mem_start, mem_end);
842
843 if (!pcibios_present()) {
844 printk("pci_init: no BIOS32 detected\n");
845 return mem_start;
846 }
847
848 printk("Probing PCI hardware.\n");
849
850 memset(&pci_root, 0, sizeof(pci_root));
851 pci_root.subordinate = scan_bus(&pci_root, &mem_start);
852
853
854 mem_start = pcibios_fixup(mem_start, mem_end);
855
856 #ifdef DEBUG
857 {
858 int len = get_pci_list((char*)mem_start);
859 if (len) {
860 ((char *) mem_start)[len] = '\0';
861 printk("%s\n", (char *) mem_start);
862 }
863 }
864 #endif
865 return mem_start;
866 }