include/asm-sparc/asi.h

/* */
This source file includes following definitions.
ldb_sun4m_bypass
ldw_sun4m_bypass
stb_sun4m_bypass
stw_sun4m_bypass
   1 /* $Id: asi.h,v 1.11 1995/11/25 02:31:11 davem Exp $ */
   2 #ifndef _SPARC_ASI_H
   3 #define _SPARC_ASI_H
   4 
   5 /* asi.h:  Address Space Identifier values for the sparc.
   6  *
   7  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   8  *
   9  * Pioneer work for sun4m: Paul Hatchman (paul@sfe.com.au)
  10  * Joint edition for sun4c+sun4m: Pete A. Zaitcev <zaitcev@ipmce.su>
  11  */
  12 
  13 /* The first batch are for the sun4c. */
  14 
  15 #define ASI_NULL1           0x00
  16 #define ASI_NULL2           0x01
  17 
  18 /* sun4c and sun4 control registers and mmu/vac ops */
  19 #define ASI_CONTROL         0x02
  20 #define ASI_SEGMAP          0x03
  21 #define ASI_PTE             0x04
  22 #define ASI_HWFLUSHSEG      0x05
  23 #define ASI_HWFLUSHPAGE     0x06
  24 #define ASI_REGMAP          0x06
  25 #define ASI_HWFLUSHCONTEXT  0x07
  26 
  27 #define ASI_USERTXT         0x08
  28 #define ASI_KERNELTXT       0x09
  29 #define ASI_USERDATA        0x0a
  30 #define ASI_KERNELDATA      0x0b
  31 
  32 /* VAC Cache flushing on sun4c and sun4 */
  33 #define ASI_FLUSHSEG        0x0c
  34 #define ASI_FLUSHPG         0x0d
  35 #define ASI_FLUSHCTX        0x0e
  36 
  37 /* SPARCstation-5: only 6 bits are decoded. */
  38 /* wo = Write Only, rw = Read Write;        */
  39 /* ss = Single Size, as = All Sizes;        */
  40 #define ASI_M_RES00         0x00   /* Don't touch... */
  41 #define ASI_M_UNA01         0x01   /* Same here... */
  42 #define ASI_M_MXCC          0x02   /* Access to TI VIKING MXCC registers */
  43 #define ASI_M_FLUSH_PROBE   0x03   /* Reference MMU Flush/Probe; rw, ss */
  44 #define ASI_M_MMUREGS       0x04   /* MMU Registers; rw, ss */
  45 #define ASI_M_TLBDIAG       0x05   /* MMU TLB only Diagnostics */
  46 #define ASI_M_DIAGS         0x06   /* Reference MMU Diagnostics */
  47 #define ASI_M_IODIAG        0x07   /* MMU I/O TLB only Diagnostics */
  48 #define ASI_M_USERTXT       0x08   /* Same as ASI_USERTXT; rw, as */
  49 #define ASI_M_KERNELTXT     0x09   /* Same as ASI_KERNELTXT; rw, as */
  50 #define ASI_M_USERDATA      0x0A   /* Same as ASI_USERDATA; rw, as */
  51 #define ASI_M_KERNELDATA    0x0B   /* Same as ASI_KERNELDATA; rw, as */
  52 #define ASI_M_TXTC_TAG      0x0C   /* Instruction Cache Tag; rw, ss */
  53 #define ASI_M_TXTC_DATA     0x0D   /* Instruction Cache Data; rw, ss */
  54 #define ASI_M_DATAC_TAG     0x0E   /* Data Cache Tag; rw, ss */
  55 #define ASI_M_DATAC_DATA    0x0F   /* Data Cache Data; rw, ss */
  56 
  57 /* The following cache flushing ASIs work only with the 'sta'
  58  * instruction. Results are unpredictable for 'swap' and 'ldstuba',
  59  * so don't do it.
  60  */
  61 
  62 /* These ASI flushes affect external caches too. */
  63 #define ASI_M_FLUSH_PAGE    0x10   /* Flush I&D Cache Line (page); wo, ss */
  64 #define ASI_M_FLUSH_SEG     0x11   /* Flush I&D Cache Line (seg); wo, ss */
  65 #define ASI_M_FLUSH_REGION  0x12   /* Flush I&D Cache Line (region); wo, ss */
  66 #define ASI_M_FLUSH_CTX     0x13   /* Flush I&D Cache Line (context); wo, ss */
  67 #define ASI_M_FLUSH_USER    0x14   /* Flush I&D Cache Line (user); wo, ss */
  68 
  69 /* Block-copy operations are available only on certain V8 cpus. */
  70 #define ASI_M_BCOPY         0x17   /* Block copy */
  71 
  72 /* These affect only the ICACHE and are Ross HyperSparc specific. */
  73 #define ASI_M_IFLUSH_PAGE   0x18   /* Flush I Cache Line (page); wo, ss */
  74 #define ASI_M_IFLUSH_SEG    0x19   /* Flush I Cache Line (seg); wo, ss */
  75 #define ASI_M_IFLUSH_REGION 0x1A   /* Flush I Cache Line (region); wo, ss */
  76 #define ASI_M_IFLUSH_CTX    0x1B   /* Flush I Cache Line (context); wo, ss */
  77 #define ASI_M_IFLUSH_USER   0x1C   /* Flush I Cache Line (user); wo, ss */
  78 
  79 /* Block-fill operations are available on certain V8 cpus */
  80 #define ASI_M_BFILL         0x1F
  81 
  82 /* This allows direct access to main memory, actually 0x20 to 0x2f are
  83  * the available ASI's for physical ram pass-through, but I don't have
  84  * any idea what the other ones do....
  85  */
  86 
  87 #define ASI_M_BYPASS       0x20   /* Reference MMU bypass; rw, as */
  88 #define ASI_M_FBMEM        0x29   /* Graphics card frame buffer access */
  89 #define ASI_M_VMEUS        0x2A   /* VME user 16-bit access */
  90 #define ASI_M_VMEPS        0x2B   /* VME priv 16-bit access */
  91 #define ASI_M_VMEUT        0x2C   /* VME user 32-bit access */
  92 #define ASI_M_VMEPT        0x2D   /* VME priv 32-bit access */
  93 #define ASI_M_SBUS         0x2E   /* Direct SBus access */
  94 #define ASI_M_CTL          0x2F   /* Control Space (ECC and MXCC are here) */
  95 
  96 
  97 /* This is ROSS HyperSparc only. */
  98 #define ASI_M_FLUSH_IWHOLE 0x31   /* Flush entire ICACHE; wo, ss */
  99 
 100 #define ASI_M_DCDR         0x39   /* Data Cache Diagnostics Registerl rw, ss */
 101 
 102 /* Sparc V9 TI UltraSparc ASI's (V8 ploos ploos) */
 103 
 104 /* ASIs 0x0-0x7f are Supervisor Only.  0x80-0xff are for anyone. */
 105 
 106 /* You will notice that there are a lot of places where if a normal
 107  * ASI is available on the V9, there is also a little-endian version.
 108  */
 109 
 110 #define ASI_V9_RESV0       0x00   /* Don't touch... */
 111 #define ASI_V9_RESV1       0x01   /* Not here */
 112 #define ASI_V9_RESV2       0x02   /* Or here */
 113 #define ASI_V9_RESV3       0x03   /* nor here. */
 114 #define ASI_V9_NUCLEUS     0x04   /* Impl-dep extra virtual access context */
 115 #define ASI_V9_NUCLEUSL    0x0C   /* Nucleus context, little-endian */
 116 #define ASI_V9_USER_PRIM   0x10   /* User primary address space */
 117 #define ASI_V9_USER_SEC    0x11   /* User secondary address space */
 118 
 119 #define ASI_V9_MMUPASS     0x14   /* OBMEM (external cache, no data cache) */
 120 #define ASI_V9_IOPASS      0x15   /* Like MMUPASS, for I/O areas (uncached) */
 121 #define ASI_V9_USER_PRIML  0x18   /* User primary addr space, lil-endian. */
 122 #define ASI_V9_USER_SECL   0x19   /* User secondary addr space, lil-endian. */
 123 #define ASI_V9_MMUPASSL    0x1C   /* OBMEM little-endian */
 124 #define ASI_V9_IOPASSL     0x1D   /* Like IOPASS but little-endian */
 125 #define ASI_V9_ATOMICQ     0x24   /* Atomic 128-bit load address space */
 126 #define ASI_V9_ATOMICQL    0x2C   /* Atomic 128-bit load little-endian */
 127 #define ASI_V9_LSTORECTL   0x45   /* ld/st control unit */
 128 #define ASI_V9_DCACHE_ENT  0x46   /* Data cache entries */
 129 #define ASI_V9_DCACHE_TAG  0x47   /* Data cache tags */
 130 #define ASI_V9_IRQDISPS    0x48   /* IRQ dispatch status registers */
 131 #define ASI_V9_IRQRECVS    0x49   /* IRQ receive status registers */
 132 #define ASI_V9_MMUREGS     0x4A   /* Spitfire MMU control register */
 133 #define ASI_V9_ESTATE      0x4B   /* Error state enable register */
 134 #define ASI_V9_ASYNC_FSR   0x4C   /* Asynchronous Fault Status reg */
 135 #define ASI_V9_ASYNC_FAR   0x4D   /* Asynchronous Fault Address reg */
 136 
 137 #define ASI_V9_ECACHE_DIAG 0x4E   /* External Cache diagnostics */
 138 
 139 #define ASI_V9_TXTMMU      0x50   /* MMU for program text */
 140 #define ASI_V9_TXTMMU_D1   0x51   /* XXX */
 141 #define ASI_V9_TXTMMU_D2   0x52   /* XXX */
 142 #define ASI_V9_TXTMMU_TDI  0x54   /* Text MMU TLB data in */
 143 #define ASI_V9_TXTMMU_TDA  0x55   /* Text MMU TLB data access */
 144 #define ASI_V9_TXTMMU_TTR  0x56   /* Text MMU TLB tag read */
 145 #define ASI_V9_TXTMMU_TDM  0x57   /* Text MMU TLB de-map */
 146 
 147 #define ASI_V9_DATAMMU     0x58   /* MMU for program data */
 148 #define ASI_V9_DATAMMU_D1  0x59   /* XXX */
 149 #define ASI_V9_DATAMMU_D2  0x5A   /* XXX */
 150 #define ASI_V9_DATAMMU_DD  0x5B   /* XXX */
 151 #define ASI_V9_DATAMMU_TDI 0x5C   /* Data MMU TLB data in */
 152 #define ASI_V9_DATAMMU_TDA 0x5D   /* Data MMU TLB data access */
 153 #define ASI_V9_DATAMMU_TTR 0x5E   /* Data MMU TLB tag read */
 154 #define ASI_V9_DATAMMU_TDM 0x5F   /* Data MMU TLB de-map */
 155 
 156 #define ASI_V9_ICACHE_D    0x66   /* Instruction cache data */
 157 #define ASI_V9_ICACHE_T    0x67   /* Instruction cache tags */
 158 #define ASI_V9_ICACHE_DEC  0x6E   /* Instruction cache decode */
 159 #define ASI_V9_ICACHE_NXT  0x6F   /* Instruction cache next ent */
 160 
 161 #define ASI_V9_HUH1        0x70   /* XXX */
 162 #define ASI_V9_HUH2        0x71   /* XXX */
 163 
 164 #define ASI_V9_ECACHE_ACC  0x76   /* External cache registers */
 165 
 166 #define ASI_V9_INTR_DISP   0x77   /* Interrupt dispatch registers */
 167 #define ASI_V9_HUH1L       0x78   /* XXX */
 168 #define ASI_V9_HUH2L       0x79   /* XXX */
 169 #define ASI_V9_INTR_RECV   0x7f   /* Interrupt Receive registers */
 170 
 171 #define ASI_V9_PRIMARY      0x80   /* Primary address space */
 172 #define ASI_V9_SECONDARY    0x81   /* Secondary address space */
 173 #define ASI_V9_PRIMARY_NF   0x82   /* Primary address space -- No Fault */
 174 #define ASI_V9_SECONDARY_NF 0x83   /* Secondary address space -- No Fault */
 175 
 176 #define ASI_V9_PRIMARYL      0x80   /* Primary address space, little-endian */
 177 #define ASI_V9_SECONDARYL    0x81   /* Secondary address space, little-endian  */
 178 #define ASI_V9_PRIMARY_NFL   0x82   /* Primary address space, No Fault, l-endian  */
 179 #define ASI_V9_SECONDARY_NFL 0x83   /* Secondary address space, No Fault, l-endian  */
 180 
 181 #define ASI_V9_XXX1        0xC0   /* XXX */
 182 #define ASI_V9_XXX2        0xC1   /* XXX */
 183 #define ASI_V9_XXX3        0xC2   /* XXX */
 184 #define ASI_V9_XXX4        0xC3   /* XXX */
 185 #define ASI_V9_XXX5        0xC4   /* XXX */
 186 #define ASI_V9_XXX6        0xC5   /* XXX */
 187 #define ASI_V9_XXX7        0xC8   /* XXX */
 188 #define ASI_V9_XXX8        0xC9   /* XXX */
 189 #define ASI_V9_XXX9        0xCA   /* XXX */
 190 #define ASI_V9_XXX10       0xCB   /* XXX */
 191 #define ASI_V9_XXX11       0xCC   /* XXX */
 192 #define ASI_V9_XXX12       0xCD   /* XXX */
 193 
 194 #define ASI_V9_XXX13       0xD0   /* XXX */
 195 #define ASI_V9_XXX14       0xD1   /* XXX */
 196 #define ASI_V9_XXX15       0xD2   /* XXX */
 197 #define ASI_V9_XXX16       0xD3   /* XXX */
 198 #define ASI_V9_XXX17       0xD8   /* XXX */
 199 #define ASI_V9_XXX18       0xD9   /* XXX */
 200 #define ASI_V9_XXX19       0xDA   /* XXX */
 201 #define ASI_V9_XXX20       0xDB   /* XXX */
 202 
 203 #define ASI_V9_XXX21       0xE0   /* XXX */
 204 #define ASI_V9_XXX22       0xE1   /* XXX */
 205 #define ASI_V9_XXX23       0xF0   /* XXX */
 206 #define ASI_V9_XXX24       0xF1   /* XXX */
 207 #define ASI_V9_XXX25       0xF8   /* XXX */
 208 #define ASI_V9_XXX26       0xF9   /* XXX */
 209 
 210 #ifndef __ASSEMBLY__
 211 
 212 /* Better to do these inline with gcc __asm__ statements. */
 213 
 214 /* The following allow you to access physical memory directly without
 215  * translation by the SRMMU.  The only other way to do this is to
 216  * turn off the SRMMU completely, and well... thats not good.
 217  *
 218  * TODO: For non-MBus SRMMU units we have to perform the following
 219  *       using this sequence.
 220  * 1) Turn off traps
 221  * 2) Turn on AC bit in SRMMU control register
 222  * 3) Do our direct physical memory access
 223  * 4) Restore old SRMMU control register value
 224  * 5) Restore old %psr value 
 225  */
 226 
 227 extern __inline__ unsigned int
 228 ldb_sun4m_bypass(unsigned int addr)
     /*  */
 229 {
 230   unsigned int retval;
 231 
 232   __asm__("lduba [%2] %1, %0\n\t" :
 233           "=r" (retval) :
 234           "i" (ASI_M_BYPASS), "r" (addr));
 235 
 236   return retval;
 237 }
 238 
 239 extern __inline__ unsigned int
 240 ldw_sun4m_bypass(unsigned int addr)
     /*  */
 241 {
 242   unsigned int retval;
 243 
 244   __asm__("lda [%2] %1, %0\n\t" :
 245           "=r" (retval) :
 246           "i" (ASI_M_BYPASS), "r" (addr));
 247 
 248   return retval;
 249 }
 250 
 251 extern __inline__ void
 252 stb_sun4m_bypass(unsigned char value, unsigned int addr)
     /*  */
 253 {
 254   __asm__("stba %0, [%2] %1\n\t" : :
 255           "r" (value), "i" (ASI_M_BYPASS), "r" (addr) :
 256           "memory");
 257 }
 258 
 259 extern __inline__ void
 260 stw_sun4m_bypass(unsigned int value, unsigned int addr)
     /*  */
 261 {
 262   __asm__("sta %0, [%2] %1\n\t" : :
 263           "r" (value), "i" (ASI_M_BYPASS), "r" (addr) :
 264           "memory");
 265 }
 266 
 267 #endif /* !(__ASSEMBLY__) */
 268 
 269 
 270 #endif /* _SPARC_ASI_H */
/* */
root/include/asm-sparc/asi.h

INCLUDED FROM

DEFINITIONS
