root/include/asm-sparc/cache.h

/* */

INCLUDED FROM

DEFINITIONS

1. get_icache_tag
2. put_icache_tag
3. get_icache_data
4. put_icache_data
5. flush_ei_page
6. flush_ei_seg
7. flush_ei_region
8. flush_ei_ctx
9. flush_ei_user

   1 /* $Id: cache.h,v 1.3 1995/11/25 02:31:22 davem Exp $
   2  * cache.h:  Cache specific code for the Sparc.  These include flushing
   3  *           and direct tag/data line access.
   4  *
   5  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   6  */
   7 
   8 #ifndef _SPARC_CACHE_H
   9 #define _SPARC_CACHE_H
  10 
  11 #include <asm/asi.h>
  12 
  13 /* Direct access to the instruction cache is provided through and
  14  * alternate address space.  The IDC bit must be off in the ICCR on
  15  * HyperSparcs for these accesses to work.  The code below does not do
  16  * any checking, the caller must do so.  These routines are for
  17  * diagnostics only, but coule end up being useful.  Use with care.
  18  * Also, you are asking for trouble if you execute these in one of the
  19  * three instructions following a %asr/%psr access or modification.
  20  */
  21 
  22 /* First, cache-tag access. */
  23 extern inline unsigned int get_icache_tag(int setnum, int tagnum)
     /*  */
  24 {
  25         unsigned int vaddr, retval;
  26 
  27         vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5);
  28         __asm__ __volatile__("lda [%1] %2, %0\n\t" :
  29                              "=r" (retval) :
  30                              "r" (vaddr), "i" (ASI_M_TXTC_TAG));
  31         return retval;
  32 }
  33 
  34 extern inline void put_icache_tag(int setnum, int tagnum, unsigned int entry)
     /*  */
  35 {
  36         unsigned int vaddr;
  37 
  38         vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5);
  39         __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
  40                              "r" (entry), "r" (vaddr), "i" (ASI_M_TXTC_TAG) :
  41                              "memory");
  42 }
  43 
  44 /* Second cache-data access.  The data is returned two-32bit quantities
  45  * at a time.
  46  */
  47 extern inline void get_icache_data(int setnum, int tagnum, int subblock,
     /*  */
  48                               unsigned int *data)
  49 {
  50         unsigned int value1, value2, vaddr;
  51 
  52         vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) |
  53                 ((subblock&0x3) << 3);
  54         __asm__ __volatile__("ldda [%2] %3, %%g2\n\t"
  55                              "or %%g0, %%g2, %0\n\t"
  56                              "or %%g0, %%g3, %1\n\t" :
  57                              "=r" (value1), "=r" (value2) :
  58                              "r" (vaddr), "i" (ASI_M_TXTC_DATA) :
  59                              "g2", "g3");
  60         data[0] = value1; data[1] = value2;
  61 }
  62 
  63 extern inline void put_icache_data(int setnum, int tagnum, int subblock,
     /*  */
  64                               unsigned int *data)
  65 {
  66         unsigned int value1, value2, vaddr;
  67 
  68         vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) |
  69                 ((subblock&0x3) << 3);
  70         value1 = data[0]; value2 = data[1];
  71         __asm__ __volatile__("or %%g0, %0, %%g2\n\t"
  72                              "or %%g0, %1, %%g3\n\t"
  73                              "stda %%g2, [%2] %3\n\t" : :
  74                              "r" (value1), "r" (value2), 
  75                              "r" (vaddr), "i" (ASI_M_TXTC_DATA) :
  76                              "g2", "g3", "memory" /* no joke */);
  77 }
  78 
  79 /* Different types of flushes with the ICACHE.  Some of the flushes
  80  * affect both the ICACHE and the external cache.  Others only clear
  81  * the ICACHE entries on the cpu itself.  V8's (most) allow
  82  * granularity of flushes on the packet (element in line), whole line,
  83  * and entire cache (ie. all lines) level.  The ICACHE only flushes are
  84  * ROSS HyperSparc specific and are in ross.h
  85  */
  86 
  87 /* Flushes which clear out both the on-chip and external caches */
  88 extern inline void flush_ei_page(unsigned int addr)
     /*  */
  89 {
  90         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
  91                              "r" (addr), "i" (ASI_M_FLUSH_PAGE) :
  92                              "memory");
  93 }
  94 
  95 extern inline void flush_ei_seg(unsigned int addr)
     /*  */
  96 {
  97         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
  98                              "r" (addr), "i" (ASI_M_FLUSH_SEG) :
  99                              "memory");
 100 }
 101 
 102 extern inline void flush_ei_region(unsigned int addr)
     /*  */
 103 {
 104         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 105                              "r" (addr), "i" (ASI_M_FLUSH_REGION) :
 106                              "memory");
 107 }
 108 
 109 extern inline void flush_ei_ctx(unsigned int addr)
     /*  */
 110 {
 111         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 112                              "r" (addr), "i" (ASI_M_FLUSH_CTX) :
 113                              "memory");
 114 }
 115 
 116 extern inline void flush_ei_user(unsigned int addr)
     /*  */
 117 {
 118         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 119                              "r" (addr), "i" (ASI_M_FLUSH_USER) :
 120                              "memory");
 121 }
 122 
 123 #endif /* !(_SPARC_CACHE_H) */

/* */