This source file includes following definitions.
- NCR5380_i386_dma_setup
- NCR5380_i386_dma_write_setup
- NCR5380_i386_dma_read_setup
- NCR5380_i386_dma_residual
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28 #ifndef NCR5380_H
29 #define NCR5380_H
30
31 #define NCR5380_PUBLIC_RELEASE 6
32 #define NCR53C400_PUBLIC_RELEASE 2
33
34 #define NDEBUG_ARBITRATION 0x1
35 #define NDEBUG_AUTOSENSE 0x2
36 #define NDEBUG_DMA 0x4
37 #define NDEBUG_HANDSHAKE 0x8
38 #define NDEBUG_INFORMATION 0x10
39 #define NDEBUG_INIT 0x20
40 #define NDEBUG_INTR 0x40
41 #define NDEBUG_LINKED 0x80
42 #define NDEBUG_MAIN 0x100
43 #define NDEBUG_NO_DATAOUT 0x200
44 #define NDEBUG_NO_WRITE 0x400
45 #define NDEBUG_PIO 0x800
46 #define NDEBUG_PSEUDO_DMA 0x1000
47 #define NDEBUG_QUEUES 0x2000
48 #define NDEBUG_RESELECTION 0x4000
49 #define NDEBUG_SELECTION 0x8000
50 #define NDEBUG_USLEEP 0x10000
51 #define NDEBUG_LAST_BYTE_SENT 0x20000
52 #define NDEBUG_RESTART_SELECT 0x40000
53 #define NDEBUG_EXTENDED 0x80000
54 #define NDEBUG_C400_PREAD 0x100000
55 #define NDEBUG_C400_PWRITE 0x200000
56 #define NDEBUG_LISTS 0x400000
57
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63
64
65 #define OUTPUT_DATA_REG 0
66 #define CURRENT_SCSI_DATA_REG 0
67
68 #define INITIATOR_COMMAND_REG 1
69 #define ICR_ASSERT_RST 0x80
70 #define ICR_ARBITRATION_PROGRESS 0x40
71 #define ICR_TRI_STATE 0x40
72 #define ICR_ARBITRATION_LOST 0x20
73 #define ICR_DIFF_ENABLE 0x20
74 #define ICR_ASSERT_ACK 0x10
75 #define ICR_ASSERT_BSY 0x08
76 #define ICR_ASSERT_SEL 0x04
77 #define ICR_ASSERT_ATN 0x02
78 #define ICR_ASSERT_DATA 0x01
79
80 #ifdef DIFFERENTIAL
81 #define ICR_BASE ICR_DIFF_ENABLE
82 #else
83 #define ICR_BASE 0
84 #endif
85
86 #define MODE_REG 2
87
88
89
90
91
92 #define MR_BLOCK_DMA_MODE 0x80
93 #define MR_TARGET 0x40
94 #define MR_ENABLE_PAR_CHECK 0x20
95 #define MR_ENABLE_PAR_INTR 0x10
96 #define MR_ENABLE_EOP_INTR 0x08
97 #define MR_MONITOR_BSY 0x04
98 #define MR_DMA_MODE 0x02
99 #define MR_ARBITRATE 0x01
100
101 #ifdef PARITY
102 #define MR_BASE MR_ENABLE_PAR_CHECK
103 #else
104 #define MR_BASE 0
105 #endif
106
107 #define TARGET_COMMAND_REG 3
108 #define TCR_LAST_BYTE_SENT 0x80
109 #define TCR_ASSERT_REQ 0x08
110 #define TCR_ASSERT_MSG 0x04
111 #define TCR_ASSERT_CD 0x02
112 #define TCR_ASSERT_IO 0x01
113
114 #define STATUS_REG 4
115
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117
118
119 #define SR_RST 0x80
120 #define SR_BSY 0x40
121 #define SR_REQ 0x20
122 #define SR_MSG 0x10
123 #define SR_CD 0x08
124 #define SR_IO 0x04
125 #define SR_SEL 0x02
126 #define SR_DBP 0x01
127
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129
130
131
132 #define SELECT_ENABLE_REG 4
133
134 #define BUS_AND_STATUS_REG 5
135 #define BASR_END_DMA_TRANSFER 0x80
136 #define BASR_DRQ 0x40
137 #define BASR_PARITY_ERROR 0x20
138 #define BASR_IRQ 0x10
139 #define BASR_PHASE_MATCH 0x08
140 #define BASR_BUSY_ERROR 0x04
141 #define BASR_ATN 0x02
142 #define BASR_ACK 0x01
143
144
145 #define START_DMA_SEND_REG 5
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150
151 #define INPUT_DATA_REG 6
152
153
154 #define START_DMA_TARGET_RECEIVE_REG 6
155
156
157 #define RESET_PARITY_INTERRUPT_REG 7
158
159
160 #define START_DMA_INITIATOR_RECEIVE_REG 7
161
162 #define C400_CONTROL_STATUS_REG NCR53C400_register_offset-8
163
164 #define CSR_RESET 0x80
165 #define CSR_53C80_REG 0x80
166 #define CSR_TRANS_DIR 0x40
167 #define CSR_SCSI_BUFF_INTR 0x20
168 #define CSR_53C80_INTR 0x10
169 #define CSR_SHARED_INTR 0x08
170 #define CSR_HOST_BUF_NOT_RDY 0x04
171 #define CSR_SCSI_BUF_RDY 0x02
172 #define CSR_GATED_53C80_IRQ 0x01
173
174 #if 0
175 #define CSR_BASE CSR_SCSI_BUFF_INTR | CSR_53C80_INTR
176 #else
177 #define CSR_BASE CSR_53C80_INTR
178 #endif
179
180
181 #define C400_BLOCK_COUNTER_REG NCR53C400_register_offset-7
182
183
184 #define C400_RESUME_TRANSFER_REG NCR53C400_register_offset-6
185
186
187 #define C400_HOST_BUFFER NCR53C400_register_offset-4
188
189
190
191 #define PHASE_MASK (SR_MSG | SR_CD | SR_IO)
192
193 #define PHASE_DATAOUT 0
194 #define PHASE_DATAIN SR_IO
195 #define PHASE_CMDOUT SR_CD
196 #define PHASE_STATIN (SR_CD | SR_IO)
197 #define PHASE_MSGOUT (SR_MSG | SR_CD)
198 #define PHASE_MSGIN (SR_MSG | SR_CD | SR_IO)
199 #define PHASE_UNKNOWN 0xff
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206
207 #define PHASE_SR_TO_TCR(phase) ((phase) >> 2)
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214
215 #define DISCONNECT_NONE 0
216 #define DISCONNECT_TIME_TO_DATA 1
217 #define DISCONNECT_LONG 2
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222
223 #define TAG_NEXT -1
224 #define TAG_NONE -2
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234 #define IRQ_NONE 255
235 #define DMA_NONE 255
236 #define IRQ_AUTO 254
237 #define DMA_AUTO 254
238
239 #define FLAG_HAS_LAST_BYTE_SENT 1
240 #define FLAG_CHECK_LAST_BYTE_SENT 2
241 #define FLAG_NCR53C400 4
242 #define FLAG_NO_PSEUDO_DMA 8
243
244 #ifndef ASM
245 struct NCR5380_hostdata {
246 NCR5380_implementation_fields;
247 unsigned char id_mask, id_higher_mask;
248 unsigned char targets_present;
249
250
251 volatile unsigned char busy[8];
252 #if defined(REAL_DMA) || defined(REAL_DMA_POLL)
253 volatile int dma_len;
254 #endif
255 volatile unsigned char last_message;
256 volatile Scsi_Cmnd *connected;
257 volatile Scsi_Cmnd *issue_queue;
258 volatile Scsi_Cmnd *disconnected_queue;
259 volatile int restart_select;
260
261
262 volatile unsigned aborted:1;
263 int flags;
264 #ifdef USLEEP
265 unsigned long time_expires;
266 struct Scsi_Host *next_timer;
267 #endif
268 #ifdef NCR5380_STATS
269 unsigned timebase;
270 long time_read[8];
271 long time_write[8];
272 unsigned long bytes_read[8];
273 unsigned long bytes_write[8];
274 unsigned pendingr;
275 unsigned pendingw;
276 #endif
277 };
278
279 #ifdef __KERNEL__
280 static struct Scsi_Host *first_instance;
281
282 #if defined(AUTOPROBE_IRQ)
283 static int NCR5380_probe_irq (struct Scsi_Host *instance, int possible);
284 #endif
285 static void NCR5380_init (struct Scsi_Host *instance, int flags);
286 static void NCR5380_information_transfer (struct Scsi_Host *instance);
287 static void NCR5380_intr (int irq, void *dev_id, struct pt_regs * regs);
288 static void NCR5380_main (void);
289 static void NCR5380_print_options (struct Scsi_Host *instance);
290 static void NCR5380_print_phase (struct Scsi_Host *instance);
291 static void NCR5380_print (struct Scsi_Host *instance);
292 #ifndef NCR5380_abort
293 static
294 #endif
295 int NCR5380_abort (Scsi_Cmnd *cmd);
296 #ifndef NCR5380_reset
297 static
298 #endif
299 int NCR5380_reset (Scsi_Cmnd *cmd);
300 #ifndef NCR5380_queue_command
301 static
302 #endif
303 int NCR5380_queue_command (Scsi_Cmnd *cmd, void (*done)(Scsi_Cmnd *));
304
305
306 static void NCR5380_reselect (struct Scsi_Host *instance);
307 static int NCR5380_select (struct Scsi_Host *instance, Scsi_Cmnd *cmd, int tag);
308 #if defined(PSEUDO_DMA) || defined(REAL_DMA) || defined(REAL_DMA_POLL)
309 static int NCR5380_transfer_dma (struct Scsi_Host *instance,
310 unsigned char *phase, int *count, unsigned char **data);
311 #endif
312 static int NCR5380_transfer_pio (struct Scsi_Host *instance,
313 unsigned char *phase, int *count, unsigned char **data);
314
315 #if (defined(REAL_DMA) || defined(REAL_DMA_POLL)) && defined(i386)
316 static __inline__ int NCR5380_i386_dma_setup (struct Scsi_Host *instance,
317 unsigned char *ptr, unsigned int count, unsigned char mode) {
318 unsigned limit;
319
320 if (instance->dma_channel <=3) {
321 if (count > 65536)
322 count = 65536;
323 limit = 65536 - (((unsigned) ptr) & 0xFFFF);
324 } else {
325 if (count > 65536 * 2)
326 count = 65536 * 2;
327 limit = 65536* 2 - (((unsigned) ptr) & 0x1FFFF);
328 }
329
330 if (count > limit) count = limit;
331
332 if ((count & 1) || (((unsigned) ptr) & 1))
333 panic ("scsi%d : attempted unaligned DMA transfer\n", instance->host_no);
334 cli();
335 disable_dma(instance->dma_channel);
336 clear_dma_ff(instance->dma_channel);
337 set_dma_addr(instance->dma_channel, (unsigned int) ptr);
338 set_dma_count(instance->dma_channel, count);
339 set_dma_mode(instance->dma_channel, mode);
340 enable_dma(instance->dma_channel);
341 sti();
342 return count;
343 }
344
345 static __inline__ int NCR5380_i386_dma_write_setup (struct Scsi_Host *instance,
346 unsigned char *src, unsigned int count) {
347 return NCR5380_i386_dma_setup (instance, src, count, DMA_MODE_WRITE);
348 }
349
350 static __inline__ int NCR5380_i386_dma_read_setup (struct Scsi_Host *instance,
351 unsigned char *src, unsigned int count) {
352 return NCR5380_i386_dma_setup (instance, src, count, DMA_MODE_READ);
353 }
354
355 static __inline__ int NCR5380_i386_dma_residual (struct Scsi_Host *instance) {
356 register int tmp;
357 cli();
358 clear_dma_ff(instance->dma_channel);
359 tmp = get_dma_residue(instance->dma_channel);
360 sti();
361 return tmp;
362 }
363 #endif
364 #endif __KERNEL_
365 #endif
366 #endif