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28 #ifndef DTC3280_H
29 #define DTC3280_H
30
31 #define DTC_PUBLIC_RELEASE 1
32
33
34 #define DTCDEBUG_INIT 0x1
35 #define DTCDEBUG_TRANSFER 0x2
36
37
38
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42
43
44
45 #define DTC_CONTROL_REG 0x100
46 #define D_CR_ACCESS 0x80
47 #define CSR_DIR_READ 0x40
48
49 #define CSR_RESET 0x80
50 #define CSR_5380_REG 0x80
51 #define CSR_TRANS_DIR 0x40
52 #define CSR_SCSI_BUFF_INTR 0x20
53 #define CSR_5380_INTR 0x10
54 #define CSR_SHARED_INTR 0x08
55 #define CSR_HOST_BUF_NOT_RDY 0x04
56 #define CSR_SCSI_BUF_RDY 0x02
57 #define CSR_GATED_5380_IRQ 0x01
58 #define CSR_INT_BASE (CSR_SCSI_BUFF_INTR | CSR_5380_INTR)
59
60
61 #define DTC_BLK_CNT 0x101
62
63
64
65 #define D_CR_ACCESS 0x80
66
67 #define DTC_SWITCH_REG 0x3982
68 #define DTC_RESUME_XFER 0x3982
69
70
71 #define DTC_5380_OFFSET 0x3880
72
73
74 #define DTC_DATA_BUF 0x3900
75
76
77 #ifndef ASM
78 int dtc_abort(Scsi_Cmnd *);
79 int dtc_biosparam(Disk *, kdev_t, int*);
80 int dtc_detect(Scsi_Host_Template *);
81 int dtc_queue_command(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
82 int dtc_reset(Scsi_Cmnd *);
83 int dtc_proc_info (char *buffer, char **start, off_t offset,
84 int length, int hostno, int inout);
85
86 #ifndef NULL
87 #define NULL 0
88 #endif
89
90 #ifndef CMD_PER_LUN
91 #define CMD_PER_LUN 2
92 #endif
93
94 #ifndef CAN_QUEUE
95 #define CAN_QUEUE 32
96 #endif
97
98
99
100
101
102
103
104 #if defined(HOSTS_C) || defined(MODULE)
105
106 #define DTC3x80 {NULL, NULL, NULL, NULL, \
107 "DTC 3180/3280 ", dtc_detect, NULL, \
108 NULL, \
109 NULL, dtc_queue_command, dtc_abort, dtc_reset, NULL, \
110 dtc_biosparam, \
111 CAN_QUEUE, 7, SG_ALL, \
112 CMD_PER_LUN , 0, 0, DISABLE_CLUSTERING}
113
114 #endif
115
116 #ifndef HOSTS_C
117
118 #define NCR5380_implementation_fields \
119 volatile unsigned char *base
120
121 #define NCR5380_local_declare() \
122 volatile unsigned char *base
123
124 #define NCR5380_setup(instance) \
125 base = (volatile unsigned char *) (instance)->base
126
127 #define DTC_address(reg) (base + DTC_5380_OFFSET + reg)
128
129 #define dbNCR5380_read(reg) \
130 (rval=*(DTC_address(reg)), \
131 (((unsigned char) printk("DTC : read register %d at addr %08x is: %02x\n"\
132 , (reg), (int)DTC_address(reg), rval)), rval ) )
133
134 #define dbNCR5380_write(reg, value) do { \
135 printk("DTC : write %02x to register %d at address %08x\n", \
136 (value), (reg), (int)DTC_address(reg)); \
137 *(DTC_address(reg)) = (value);} while(0)
138
139
140 #if !(DTCDEBUG & DTCDEBUG_TRANSFER)
141 #define NCR5380_read(reg) (*(DTC_address(reg)))
142 #define NCR5380_write(reg, value) (*(DTC_address(reg)) = (value))
143 #else
144 #define NCR5380_read(reg) (*(DTC_address(reg)))
145 #define xNCR5380_read(reg) \
146 (((unsigned char) printk("DTC : read register %d at address %08x\n"\
147 , (reg), DTC_address(reg))), *(DTC_address(reg)))
148
149 #define NCR5380_write(reg, value) do { \
150 printk("DTC : write %02x to register %d at address %08x\n", \
151 (value), (reg), (int)DTC_address(reg)); \
152 *(DTC_address(reg)) = (value); } while(0)
153 #endif
154
155 #define NCR5380_intr dtc_intr
156 #define NCR5380_queue_command dtc_queue_command
157 #define NCR5380_abort dtc_abort
158 #define NCR5380_reset dtc_reset
159 #define NCR5380_proc_info dtc_proc_info
160
161
162
163
164 #define DTC_IRQS 0x9c00
165
166
167 #endif
168 #endif
169 #endif