This source file includes following definitions.
- ewrk3_probe
- ewrk3_hw_init
- ewrk3_open
- ewrk3_init
- ewrk3_queue_pkt
- ewrk3_interrupt
- ewrk3_rx
- ewrk3_tx
- ewrk3_close
- ewrk3_get_stats
- set_multicast_list
- SetMulticastFilter
- isa_probe
- eisa_probe
- alloc_device
- Read_EEPROM
- Write_EEPROM
- EthwrkSignature
- DevicePresent
- get_hw_addr
- EISA_signature
- ewrk3_ioctl
- init_module
- cleanup_module
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140 static const char *version = "ewrk3.c:v0.42 96/4/22 davies@wanton.lkg.dec.com\n";
141
142 #include <linux/module.h>
143
144 #include <linux/kernel.h>
145 #include <linux/sched.h>
146 #include <linux/string.h>
147 #include <linux/ptrace.h>
148 #include <linux/errno.h>
149 #include <linux/ioport.h>
150 #include <linux/malloc.h>
151 #include <linux/interrupt.h>
152 #include <linux/delay.h>
153 #include <asm/bitops.h>
154 #include <asm/io.h>
155 #include <asm/dma.h>
156 #include <asm/segment.h>
157
158 #include <linux/netdevice.h>
159 #include <linux/etherdevice.h>
160 #include <linux/skbuff.h>
161
162 #include <linux/time.h>
163 #include <linux/types.h>
164 #include <linux/unistd.h>
165
166 #include "ewrk3.h"
167
168 #ifdef EWRK3_DEBUG
169 static int ewrk3_debug = EWRK3_DEBUG;
170 #else
171 static int ewrk3_debug = 1;
172 #endif
173
174 #define EWRK3_NDA 0xffe0
175
176 #define PROBE_LENGTH 32
177 #define ETH_PROM_SIG 0xAA5500FFUL
178
179 #ifndef EWRK3_SIGNATURE
180 #define EWRK3_SIGNATURE {"DE203","DE204","DE205",""}
181 #define EWRK3_STRLEN 8
182 #endif
183
184 #ifndef EWRK3_RAM_BASE_ADDRESSES
185 #define EWRK3_RAM_BASE_ADDRESSES {0xc0000,0xd0000,0x00000}
186 #endif
187
188
189
190
191 #define EWRK3_IO_BASE 0x100
192 #define EWRK3_IOP_INC 0x20
193 #define EWRK3_TOTAL_SIZE 0x20
194
195 #ifndef MAX_NUM_EWRK3S
196 #define MAX_NUM_EWRK3S 21
197 #endif
198
199 #ifndef EWRK3_EISA_IO_PORTS
200 #define EWRK3_EISA_IO_PORTS 0x0c00
201 #endif
202
203 #ifndef MAX_EISA_SLOTS
204 #define MAX_EISA_SLOTS 16
205 #define EISA_SLOT_INC 0x1000
206 #endif
207
208 #define CRC_POLYNOMIAL_BE 0x04c11db7UL
209 #define CRC_POLYNOMIAL_LE 0xedb88320UL
210
211 #define QUEUE_PKT_TIMEOUT (1*HZ)
212
213
214
215
216 #define IO_ONLY 0x00
217 #define SHMEM_2K 0x800
218 #define SHMEM_32K 0x8000
219 #define SHMEM_64K 0x10000
220
221
222
223
224 #define ENABLE_IRQs { \
225 icr |= lp->irq_mask;\
226 outb(icr, EWRK3_ICR); \
227 }
228
229 #define DISABLE_IRQs { \
230 icr = inb(EWRK3_ICR);\
231 icr &= ~lp->irq_mask;\
232 outb(icr, EWRK3_ICR); \
233 }
234
235
236
237
238 #define START_EWRK3 { \
239 csr = inb(EWRK3_CSR);\
240 csr &= ~(CSR_TXD|CSR_RXD);\
241 outb(csr, EWRK3_CSR); \
242 }
243
244 #define STOP_EWRK3 { \
245 csr = (CSR_TXD|CSR_RXD);\
246 outb(csr, EWRK3_CSR); \
247 }
248
249
250
251
252 #define EWRK3_PKT_STAT_SZ 16
253 #define EWRK3_PKT_BIN_SZ 128
254
255
256 struct ewrk3_private {
257 char adapter_name[80];
258 u_long shmem_base;
259 u_long shmem_length;
260 struct enet_statistics stats;
261 struct {
262 u32 bins[EWRK3_PKT_STAT_SZ];
263 u32 unicast;
264 u32 multicast;
265 u32 broadcast;
266 u32 excessive_collisions;
267 u32 tx_underruns;
268 u32 excessive_underruns;
269 } pktStats;
270 u_char irq_mask;
271 u_char mPage;
272 u_char lemac;
273 u_char hard_strapped;
274 u_char lock;
275 u_char txc;
276 u_char *mctbl;
277 };
278
279
280
281
282 #define FORCE_2K_MODE { \
283 shmem_length = SHMEM_2K;\
284 outb(((mem_start - 0x80000) >> 11), EWRK3_MBR);\
285 }
286
287
288
289
290 static int ewrk3_open(struct device *dev);
291 static int ewrk3_queue_pkt(struct sk_buff *skb, struct device *dev);
292 static void ewrk3_interrupt(int irq, void *dev_id, struct pt_regs *regs);
293 static int ewrk3_close(struct device *dev);
294 static struct enet_statistics *ewrk3_get_stats(struct device *dev);
295 static void set_multicast_list(struct device *dev);
296 static int ewrk3_ioctl(struct device *dev, struct ifreq *rq, int cmd);
297
298
299
300
301 static int ewrk3_hw_init(struct device *dev, u_long iobase);
302 static void ewrk3_init(struct device *dev);
303 static int ewrk3_rx(struct device *dev);
304 static int ewrk3_tx(struct device *dev);
305
306 static void EthwrkSignature(char * name, char *eeprom_image);
307 static int DevicePresent(u_long iobase);
308 static void SetMulticastFilter(struct device *dev);
309 static int EISA_signature(char *name, s32 eisa_id);
310
311 static int Read_EEPROM(u_long iobase, u_char eaddr);
312 static int Write_EEPROM(short data, u_long iobase, u_char eaddr);
313 static u_char get_hw_addr (struct device *dev, u_char *eeprom_image, char chipType);
314
315 static void isa_probe(struct device *dev, u_long iobase);
316 static void eisa_probe(struct device *dev, u_long iobase);
317 static struct device *alloc_device(struct device *dev, u_long iobase);
318
319
320 #ifdef MODULE
321 int init_module(void);
322 void cleanup_module(void);
323 static int autoprobed = 1, loading_module = 1;
324
325 # else
326 static u_char irq[] = {5,0,10,3,11,9,15,12};
327 static int autoprobed = 0, loading_module = 0;
328
329 #endif
330
331 static char name[EWRK3_STRLEN + 1];
332 static int num_ewrk3s = 0, num_eth = 0;
333
334
335
336
337 #define INIT_EWRK3 {\
338 outb(EEPROM_INIT, EWRK3_IOPR);\
339 udelay(1000);\
340 }
341
342
343
344
345 int ewrk3_probe(struct device *dev)
346 {
347 int tmp = num_ewrk3s, status = -ENODEV;
348 u_long iobase = dev->base_addr;
349
350 if ((iobase == 0) && loading_module){
351 printk("Autoprobing is not supported when loading a module based driver.\n");
352 status = -EIO;
353 } else {
354
355 isa_probe(dev, iobase);
356 eisa_probe(dev, iobase);
357
358 if ((tmp == num_ewrk3s) && (iobase != 0) && loading_module) {
359 printk("%s: ewrk3_probe() cannot find device at 0x%04lx.\n", dev->name,
360 iobase);
361 }
362
363
364
365
366
367 for (; (dev->priv == NULL) && (dev->next != NULL); dev = dev->next);
368
369 if (dev->priv) status = 0;
370 if (iobase == 0) autoprobed = 1;
371 }
372
373 return status;
374 }
375
376 static int
377 ewrk3_hw_init(struct device *dev, u_long iobase)
378 {
379 struct ewrk3_private *lp;
380 int i, status=0;
381 u_long mem_start, shmem_length;
382 u_char cr, cmr, icr, nicsr, lemac, hard_strapped = 0;
383 u_char eeprom_image[EEPROM_MAX], chksum, eisa_cr = 0;
384
385
386
387
388
389 if (iobase > 0x400) eisa_cr = inb(EISA_CR);
390 INIT_EWRK3;
391
392 nicsr = inb(EWRK3_CSR);
393
394 icr = inb(EWRK3_ICR);
395 icr &= 0x70;
396 outb(icr, EWRK3_ICR);
397
398 if (nicsr == (CSR_TXD|CSR_RXD)) {
399
400
401 for (chksum=0, i=0; i<EEPROM_MAX; i+=2) {
402 union {
403 short val;
404 char c[2];
405 } tmp;
406
407 tmp.val = (short)Read_EEPROM(iobase, (i>>1));
408 eeprom_image[i] = tmp.c[0];
409 eeprom_image[i+1] = tmp.c[1];
410 chksum += eeprom_image[i] + eeprom_image[i+1];
411 }
412
413 if (chksum != 0) {
414 printk("%s: Device has a bad on-board EEPROM.\n", dev->name);
415 status = -ENXIO;
416 } else {
417 EthwrkSignature(name, eeprom_image);
418 if (*name != '\0') {
419 dev->base_addr = iobase;
420
421 if (iobase > 0x400) {
422 outb(eisa_cr, EISA_CR);
423 }
424
425 lemac = eeprom_image[EEPROM_CHIPVER];
426 cmr = inb(EWRK3_CMR);
427
428 if (((lemac == LeMAC) && ((cmr & CMR_NO_EEPROM) != CMR_NO_EEPROM)) ||
429 ((lemac == LeMAC2) && !(cmr & CMR_HS))) {
430 printk("%s: %s at %#4lx", dev->name, name, iobase);
431 hard_strapped = 1;
432 } else if ((iobase&0x0fff)==EWRK3_EISA_IO_PORTS) {
433
434 printk("%s: %s at %#4lx (EISA slot %ld)",
435 dev->name, name, iobase, ((iobase>>12)&0x0f));
436 } else {
437 printk("%s: %s at %#4lx", dev->name, name, iobase);
438 }
439
440 if (!status) {
441 printk(", h/w address ");
442 if (lemac!=LeMAC2) DevicePresent(iobase);
443 status = get_hw_addr(dev, eeprom_image, lemac);
444 for (i = 0; i < ETH_ALEN - 1; i++) {
445 printk("%2.2x:", dev->dev_addr[i]);
446 }
447 printk("%2.2x,\n", dev->dev_addr[i]);
448
449 if (status) {
450 printk(" which has an EEPROM CRC error.\n");
451 status = -ENXIO;
452 } else {
453 if (lemac == LeMAC2) {
454 cmr &= ~(CMR_RA | CMR_WB | CMR_LINK | CMR_POLARITY | CMR_0WS);
455 if (eeprom_image[EEPROM_MISC0] & READ_AHEAD) cmr |= CMR_RA;
456 if (eeprom_image[EEPROM_MISC0] & WRITE_BEHIND) cmr |= CMR_WB;
457 if (eeprom_image[EEPROM_NETMAN0] & NETMAN_POL) cmr |= CMR_POLARITY;
458 if (eeprom_image[EEPROM_NETMAN0] & NETMAN_LINK) cmr |= CMR_LINK;
459 if (eeprom_image[EEPROM_MISC0] & _0WS_ENA) cmr |= CMR_0WS;
460 }
461 if (eeprom_image[EEPROM_SETUP] & SETUP_DRAM) cmr |= CMR_DRAM;
462 outb(cmr, EWRK3_CMR);
463
464 cr = inb(EWRK3_CR);
465 cr |= eeprom_image[EEPROM_SETUP] & SETUP_APD;
466 if (cr & SETUP_APD) cr |= eeprom_image[EEPROM_SETUP] & SETUP_PS;
467 cr |= eeprom_image[EEPROM_MISC0] & FAST_BUS;
468 cr |= eeprom_image[EEPROM_MISC0] & ENA_16;
469 outb(cr, EWRK3_CR);
470
471
472
473
474
475 mem_start = inb(EWRK3_MBR);
476 shmem_length = 0;
477 if (mem_start != 0) {
478 if ((mem_start >= 0x0a) && (mem_start <= 0x0f)) {
479 mem_start *= SHMEM_64K;
480 shmem_length = SHMEM_64K;
481 } else if ((mem_start >= 0x14) && (mem_start <= 0x1f)) {
482 mem_start *= SHMEM_32K;
483 shmem_length = SHMEM_32K;
484 } else if ((mem_start >= 0x40) && (mem_start <= 0xff)) {
485 mem_start = mem_start * SHMEM_2K + 0x80000;
486 shmem_length = SHMEM_2K;
487 } else {
488 status = -ENXIO;
489 }
490 }
491
492
493
494
495
496
497
498 if (!status) {
499 if (hard_strapped) {
500 printk(" is hard strapped.\n");
501 } else if (mem_start) {
502 printk(" has a %dk RAM window", (int)(shmem_length >> 10));
503 printk(" at 0x%.5lx", mem_start);
504 } else {
505 printk(" is in I/O only mode");
506 }
507
508
509 dev->priv = (void *) kmalloc(sizeof(struct ewrk3_private),
510 GFP_KERNEL);
511 if (dev->priv == NULL) {
512 return -ENOMEM;
513 }
514 lp = (struct ewrk3_private *)dev->priv;
515 memset(dev->priv, 0, sizeof(struct ewrk3_private));
516 lp->shmem_base = mem_start;
517 lp->shmem_length = shmem_length;
518 lp->lemac = lemac;
519 lp->hard_strapped = hard_strapped;
520
521 lp->mPage = 64;
522 if (cmr & CMR_DRAM) lp->mPage <<= 1 ;
523
524 sprintf(lp->adapter_name,"%s (%s)", name, dev->name);
525 request_region(iobase, EWRK3_TOTAL_SIZE, lp->adapter_name);
526
527 lp->irq_mask = ICR_TNEM|ICR_TXDM|ICR_RNEM|ICR_RXDM;
528
529 if (!hard_strapped) {
530
531
532
533 icr |= ICR_IE;
534 outb(icr, EWRK3_ICR);
535
536
537 dev->dma = 0;
538
539
540
541 if (dev->irq < 2) {
542 #ifndef MODULE
543 u_char irqnum;
544
545 autoirq_setup(0);
546
547
548
549
550 icr |=ICR_TNEM;
551 outb(1,EWRK3_TDQ);
552 outb(icr, EWRK3_ICR);
553
554 irqnum = irq[((icr & IRQ_SEL) >> 4)];
555
556 dev->irq = autoirq_report(1);
557 if ((dev->irq) && (irqnum == dev->irq)) {
558 printk(" and uses IRQ%d.\n", dev->irq);
559 } else {
560 if (!dev->irq) {
561 printk(" and failed to detect IRQ line.\n");
562 } else if ((irqnum == 1) && (lemac == LeMAC2)) {
563 printk(" and an illegal IRQ line detected.\n");
564 } else {
565 printk(", but incorrect IRQ line detected.\n");
566 }
567 status = -ENXIO;
568 }
569
570 DISABLE_IRQs;
571
572 #endif
573 } else {
574 printk(" and requires IRQ%d.\n", dev->irq);
575 }
576 }
577 if (status) release_region(iobase, EWRK3_TOTAL_SIZE);
578 } else {
579 status = -ENXIO;
580 }
581 }
582 }
583 } else {
584 status = -ENXIO;
585 }
586 }
587
588 if (!status) {
589 if (ewrk3_debug > 0) {
590 printk(version);
591 }
592
593
594 dev->open = &ewrk3_open;
595 dev->hard_start_xmit = &ewrk3_queue_pkt;
596 dev->stop = &ewrk3_close;
597 dev->get_stats = &ewrk3_get_stats;
598 dev->set_multicast_list = &set_multicast_list;
599 dev->do_ioctl = &ewrk3_ioctl;
600
601 dev->mem_start = 0;
602
603
604 ether_setup(dev);
605 }
606 } else {
607 status = -ENXIO;
608 }
609
610 return status;
611 }
612
613
614 static int
615 ewrk3_open(struct device *dev)
616 {
617 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
618 u_long iobase = dev->base_addr;
619 int i, status = 0;
620 u_char icr, csr;
621
622
623
624
625 STOP_EWRK3;
626
627 if (!lp->hard_strapped) {
628 irq2dev_map[dev->irq] = dev;
629
630 if (request_irq(dev->irq, (void *)ewrk3_interrupt, 0, "ewrk3", NULL)) {
631 printk("ewrk3_open(): Requested IRQ%d is busy\n",dev->irq);
632 status = -EAGAIN;
633 } else {
634
635
636
637
638 ewrk3_init(dev);
639
640 if (ewrk3_debug > 1){
641 printk("%s: ewrk3 open with irq %d\n",dev->name,dev->irq);
642 printk(" physical address: ");
643 for (i=0;i<5;i++){
644 printk("%2.2x:",(u_char)dev->dev_addr[i]);
645 }
646 printk("%2.2x\n",(u_char)dev->dev_addr[i]);
647 if (lp->shmem_length == 0) {
648 printk(" no shared memory, I/O only mode\n");
649 } else {
650 printk(" start of shared memory: 0x%08lx\n",lp->shmem_base);
651 printk(" window length: 0x%04lx\n",lp->shmem_length);
652 }
653 printk(" # of DRAMS: %d\n",((inb(EWRK3_CMR) & 0x02) ? 2 : 1));
654 printk(" csr: 0x%02x\n", inb(EWRK3_CSR));
655 printk(" cr: 0x%02x\n", inb(EWRK3_CR));
656 printk(" icr: 0x%02x\n", inb(EWRK3_ICR));
657 printk(" cmr: 0x%02x\n", inb(EWRK3_CMR));
658 printk(" fmqc: 0x%02x\n", inb(EWRK3_FMQC));
659 }
660
661 dev->tbusy = 0;
662 dev->start = 1;
663 dev->interrupt = UNMASK_INTERRUPTS;
664
665
666
667
668 icr = inb(EWRK3_ICR);
669 ENABLE_IRQs;
670
671 }
672 } else {
673 dev->start = 0;
674 dev->tbusy = 1;
675 printk("%s: ewrk3 available for hard strapped set up only.\n", dev->name);
676 printk(" Run the 'ewrk3setup' utility or remove the hard straps.\n");
677 }
678
679 MOD_INC_USE_COUNT;
680
681 return status;
682 }
683
684
685
686
687 static void
688 ewrk3_init(struct device *dev)
689 {
690 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
691 u_char csr, page;
692 u_long iobase = dev->base_addr;
693
694
695
696
697 set_multicast_list(dev);
698
699
700
701
702 while (inb(EWRK3_TQ));
703 while (inb(EWRK3_TDQ));
704 while (inb(EWRK3_RQ));
705 while (inb(EWRK3_FMQ));
706
707
708
709
710 for (page=1;page<lp->mPage;page++) {
711 outb(page, EWRK3_FMQ);
712 }
713
714 lp->lock = 0;
715
716 START_EWRK3;
717 }
718
719
720
721
722 static int
723 ewrk3_queue_pkt(struct sk_buff *skb, struct device *dev)
724 {
725 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
726 u_long iobase = dev->base_addr;
727 int status = 0;
728 u_char icr, csr;
729
730
731 if (dev->tbusy || lp->lock) {
732 int tickssofar = jiffies - dev->trans_start;
733 if (tickssofar < QUEUE_PKT_TIMEOUT) {
734 status = -1;
735 } else if (!lp->hard_strapped) {
736 printk("%s: transmit timed/locked out, status %04x, resetting.\n",
737 dev->name, inb(EWRK3_CSR));
738
739
740
741
742 DISABLE_IRQs;
743
744
745
746
747 STOP_EWRK3;
748
749 ewrk3_init(dev);
750
751
752
753
754 ENABLE_IRQs;
755
756 dev->tbusy=0;
757 dev->trans_start = jiffies;
758 }
759 } else if (skb == NULL) {
760 dev_tint(dev);
761 } else if (skb->len > 0) {
762
763
764
765
766
767 if (set_bit(0, (void*)&dev->tbusy) != 0)
768 printk("%s: Transmitter access conflict.\n", dev->name);
769
770 DISABLE_IRQs;
771
772
773
774
775 if (inb(EWRK3_FMQC) > 0) {
776 u_long buf = 0;
777 u_char page;
778
779 if ((page = inb(EWRK3_FMQ)) < lp->mPage) {
780
781
782
783 while (set_bit(0, (void *)&lp->lock) != 0);
784 if (lp->shmem_length == IO_ONLY) {
785 outb(page, EWRK3_IOPR);
786 } else if (lp->shmem_length == SHMEM_2K) {
787 buf = lp->shmem_base;
788 outb(page, EWRK3_MPR);
789 } else if (lp->shmem_length == SHMEM_32K) {
790 buf = ((((short)page << 11) & 0x7800) + lp->shmem_base);
791 outb((page >> 4), EWRK3_MPR);
792 } else if (lp->shmem_length == SHMEM_64K) {
793 buf = ((((short)page << 11) & 0xf800) + lp->shmem_base);
794 outb((page >> 5), EWRK3_MPR);
795 } else {
796 status = -1;
797 printk("%s: Oops - your private data area is hosed!\n",dev->name);
798 }
799
800 if (!status) {
801
802
803
804
805
806
807 if (lp->shmem_length == IO_ONLY) {
808 int i;
809 u_char *p = skb->data;
810
811 outb((char)(TCR_QMODE | TCR_PAD | TCR_IFC), EWRK3_DATA);
812 outb((char)(skb->len & 0xff), EWRK3_DATA);
813 outb((char)((skb->len >> 8) & 0xff), EWRK3_DATA);
814 outb((char)0x04, EWRK3_DATA);
815 for (i=0; i<skb->len; i++) {
816 outb(*p++, EWRK3_DATA);
817 }
818 outb(page, EWRK3_TQ);
819 } else {
820 writeb((char)(TCR_QMODE|TCR_PAD|TCR_IFC), (char *)buf);
821 buf+=1;
822 writeb((char)(skb->len & 0xff), (char *)buf);
823 buf+=1;
824 if (lp->txc) {
825 writeb((char)(((skb->len >> 8) & 0xff) | XCT), (char *)buf);
826 buf+=1;
827 writeb(0x04, (char *)buf);
828 buf+=1;
829 writeb(0x00, (char *)(buf + skb->len));
830 memcpy_toio(buf, skb->data, PRELOAD);
831 outb(page, EWRK3_TQ);
832 memcpy_toio(buf+PRELOAD, skb->data+PRELOAD, skb->len-PRELOAD);
833 writeb(0xff, (char *)(buf + skb->len));
834 } else {
835 writeb((char)((skb->len >> 8) & 0xff), (char *)buf);
836 buf+=1;
837 writeb(0x04, (char *)buf);
838 buf+=1;
839 memcpy_toio((char *)buf, skb->data, skb->len);
840 outb(page, EWRK3_TQ);
841 }
842 }
843
844 dev->trans_start = jiffies;
845 dev_kfree_skb (skb, FREE_WRITE);
846
847 } else {
848 outb(page, EWRK3_FMQ);
849 }
850 lp->lock = 0;
851 } else {
852 printk("ewrk3_queue_pkt(): Invalid free memory page (%d).\n",
853 (u_char) page);
854 }
855 } else {
856 printk("ewrk3_queue_pkt(): No free resources...\n");
857 printk("ewrk3_queue_pkt(): CSR: %02x ICR: %02x FMQC: %02x\n",inb(EWRK3_CSR),inb(EWRK3_ICR),inb(EWRK3_FMQC));
858 }
859
860
861 if (inb(EWRK3_FMQC) > 0) {
862 dev->tbusy = 0;
863 }
864
865 ENABLE_IRQs;
866 }
867
868 return status;
869 }
870
871
872
873
874 static void
875 ewrk3_interrupt(int irq, void *dev_id, struct pt_regs * regs)
876 {
877 struct device *dev = (struct device *)(irq2dev_map[irq]);
878 struct ewrk3_private *lp;
879 u_long iobase;
880 u_char icr, cr, csr;
881
882 if (dev == NULL) {
883 printk ("ewrk3_interrupt(): irq %d for unknown device.\n", irq);
884 } else {
885 lp = (struct ewrk3_private *)dev->priv;
886 iobase = dev->base_addr;
887
888 if (dev->interrupt)
889 printk("%s: Re-entering the interrupt handler.\n", dev->name);
890
891 dev->interrupt = MASK_INTERRUPTS;
892
893
894 csr = inb(EWRK3_CSR);
895
896
897
898
899 DISABLE_IRQs;
900
901 cr = inb(EWRK3_CR);
902 cr |= CR_LED;
903 outb(cr, EWRK3_CR);
904
905 if (csr & CSR_RNE)
906 ewrk3_rx(dev);
907
908 if (csr & CSR_TNE)
909 ewrk3_tx(dev);
910
911
912
913
914
915
916
917 if (inb(EWRK3_FMQC)) {
918 lp->irq_mask |= ICR_TXDM|ICR_RXDM;
919 csr &= ~(CSR_TXD|CSR_RXD);
920 outb(csr, EWRK3_CSR);
921 dev->tbusy = 0;
922 mark_bh(NET_BH);
923 } else {
924 lp->irq_mask &= ~(ICR_TXDM|ICR_RXDM);
925 }
926
927
928 cr &= ~CR_LED;
929 outb(cr, EWRK3_CR);
930
931 dev->interrupt = UNMASK_INTERRUPTS;
932 ENABLE_IRQs;
933 }
934
935 return;
936 }
937
938 static int
939 ewrk3_rx(struct device *dev)
940 {
941 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
942 u_long iobase = dev->base_addr;
943 int i, status = 0;
944 u_char page, tmpPage = 0, tmpLock = 0;
945 u_long buf = 0;
946
947 while (inb(EWRK3_RQC) && !status) {
948 if ((page = inb(EWRK3_RQ)) < lp->mPage) {
949
950
951
952
953 if ((tmpLock = set_bit(0, (void *)&lp->lock)) == 1) {
954 if (lp->shmem_length == IO_ONLY) {
955 tmpPage = inb(EWRK3_IOPR);
956 } else {
957 tmpPage = inb(EWRK3_MPR);
958 }
959 }
960
961
962
963
964 if (lp->shmem_length == IO_ONLY) {
965 outb(page, EWRK3_IOPR);
966 } else if (lp->shmem_length == SHMEM_2K) {
967 buf = lp->shmem_base;
968 outb(page, EWRK3_MPR);
969 } else if (lp->shmem_length == SHMEM_32K) {
970 buf = ((((short)page << 11) & 0x7800) + lp->shmem_base);
971 outb((page >> 4), EWRK3_MPR);
972 } else if (lp->shmem_length == SHMEM_64K) {
973 buf = ((((short)page << 11) & 0xf800) + lp->shmem_base);
974 outb((page >> 5), EWRK3_MPR);
975 } else {
976 status = -1;
977 printk("%s: Oops - your private data area is hosed!\n",dev->name);
978 }
979
980 if (!status) {
981 char rx_status;
982 int pkt_len;
983
984 if (lp->shmem_length == IO_ONLY) {
985 rx_status = inb(EWRK3_DATA);
986 pkt_len = inb(EWRK3_DATA);
987 pkt_len |= ((u_short)inb(EWRK3_DATA) << 8);
988 } else {
989 rx_status = readb(buf);
990 buf+=1;
991 pkt_len = readw(buf);
992 buf+=3;
993 }
994
995 if (!(rx_status & R_ROK)) {
996 lp->stats.rx_errors++;
997 if (rx_status & R_DBE) lp->stats.rx_frame_errors++;
998 if (rx_status & R_CRC) lp->stats.rx_crc_errors++;
999 if (rx_status & R_PLL) lp->stats.rx_fifo_errors++;
1000 } else {
1001 struct sk_buff *skb;
1002
1003 if ((skb = dev_alloc_skb(pkt_len+2)) != NULL) {
1004 unsigned char *p;
1005 skb->dev = dev;
1006 skb_reserve(skb,2);
1007 p = skb_put(skb,pkt_len);
1008
1009 if (lp->shmem_length == IO_ONLY) {
1010 *p = inb(EWRK3_DATA);
1011 for (i=0; i<pkt_len; i++) {
1012 *p++ = inb(EWRK3_DATA);
1013 }
1014 } else {
1015 memcpy_fromio(p, buf, pkt_len);
1016 }
1017
1018
1019
1020
1021
1022 skb->protocol=eth_type_trans(skb,dev);
1023 netif_rx(skb);
1024
1025
1026
1027
1028 lp->stats.rx_packets++;
1029 for (i=1; i<EWRK3_PKT_STAT_SZ-1; i++) {
1030 if (pkt_len < i*EWRK3_PKT_BIN_SZ) {
1031 lp->pktStats.bins[i]++;
1032 i = EWRK3_PKT_STAT_SZ;
1033 }
1034 }
1035 p = skb->data;
1036 if (p[0] & 0x01) {
1037 if ((*(s32 *)&p[0] == -1) && (*(s16 *)&p[4] == -1)) {
1038 lp->pktStats.broadcast++;
1039 } else {
1040 lp->pktStats.multicast++;
1041 }
1042 } else if ((*(s32 *)&p[0] == *(s32 *)&dev->dev_addr[0]) &&
1043 (*(s16 *)&p[4] == *(s16 *)&dev->dev_addr[4])) {
1044 lp->pktStats.unicast++;
1045 }
1046
1047 lp->pktStats.bins[0]++;
1048 if (lp->pktStats.bins[0] == 0) {
1049 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
1050 }
1051 } else {
1052 printk("%s: Insufficient memory; nuking packet.\n", dev->name);
1053 lp->stats.rx_dropped++;
1054 break;
1055 }
1056 }
1057 }
1058
1059
1060
1061 outb(page, EWRK3_FMQ);
1062
1063 if (tmpLock) {
1064 if (lp->shmem_length == IO_ONLY) {
1065 outb(tmpPage, EWRK3_IOPR);
1066 } else {
1067 outb(tmpPage, EWRK3_MPR);
1068 }
1069 }
1070 lp->lock = 0;
1071 } else {
1072 printk("ewrk3_rx(): Illegal page number, page %d\n",page);
1073 printk("ewrk3_rx(): CSR: %02x ICR: %02x FMQC: %02x\n",inb(EWRK3_CSR),inb(EWRK3_ICR),inb(EWRK3_FMQC));
1074 }
1075 }
1076 return status;
1077 }
1078
1079
1080
1081
1082 static int
1083 ewrk3_tx(struct device *dev)
1084 {
1085 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1086 u_long iobase = dev->base_addr;
1087 u_char tx_status;
1088
1089 while ((tx_status = inb(EWRK3_TDQ)) > 0) {
1090 if (tx_status & T_VSTS) {
1091 if (tx_status & T_TXE) {
1092 lp->stats.tx_errors++;
1093 if (tx_status & T_NCL) lp->stats.tx_carrier_errors++;
1094 if (tx_status & T_LCL) lp->stats.tx_window_errors++;
1095 if (tx_status & T_CTU) {
1096 if ((tx_status & T_COLL) ^ T_XUR) {
1097 lp->pktStats.tx_underruns++;
1098 } else {
1099 lp->pktStats.excessive_underruns++;
1100 }
1101 } else if (tx_status & T_COLL) {
1102 if ((tx_status & T_COLL) ^ T_XCOLL) {
1103 lp->stats.collisions++;
1104 } else {
1105 lp->pktStats.excessive_collisions++;
1106 }
1107 }
1108 } else {
1109 lp->stats.tx_packets++;
1110 }
1111 }
1112 }
1113
1114 return 0;
1115 }
1116
1117 static int
1118 ewrk3_close(struct device *dev)
1119 {
1120 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1121 u_long iobase = dev->base_addr;
1122 u_char icr, csr;
1123
1124 dev->start = 0;
1125 dev->tbusy = 1;
1126
1127 if (ewrk3_debug > 1) {
1128 printk("%s: Shutting down ethercard, status was %2.2x.\n",
1129 dev->name, inb(EWRK3_CSR));
1130 }
1131
1132
1133
1134
1135 DISABLE_IRQs;
1136
1137 STOP_EWRK3;
1138
1139
1140
1141
1142
1143
1144
1145 while (inb(EWRK3_TQ));
1146 while (inb(EWRK3_TDQ));
1147 while (inb(EWRK3_RQ));
1148
1149 if (!lp->hard_strapped) {
1150 free_irq(dev->irq, NULL);
1151
1152 irq2dev_map[dev->irq] = 0;
1153 }
1154
1155 MOD_DEC_USE_COUNT;
1156
1157 return 0;
1158 }
1159
1160 static struct enet_statistics *
1161 ewrk3_get_stats(struct device *dev)
1162 {
1163 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1164
1165
1166
1167 return &lp->stats;
1168 }
1169
1170
1171
1172
1173 static void
1174 set_multicast_list(struct device *dev)
1175 {
1176 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1177 u_long iobase = dev->base_addr;
1178 u_char csr;
1179
1180 if (irq2dev_map[dev->irq] != NULL) {
1181 csr = inb(EWRK3_CSR);
1182
1183 if (lp->shmem_length == IO_ONLY) {
1184 lp->mctbl = (char *) PAGE0_HTE;
1185 } else {
1186 lp->mctbl = (char *)(lp->shmem_base + PAGE0_HTE);
1187 }
1188
1189 csr &= ~(CSR_PME | CSR_MCE);
1190 if (dev->flags & IFF_PROMISC) {
1191 csr |= CSR_PME;
1192 outb(csr, EWRK3_CSR);
1193 } else {
1194 SetMulticastFilter(dev);
1195 csr |= CSR_MCE;
1196 outb(csr, EWRK3_CSR);
1197 }
1198 }
1199 }
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209 static void SetMulticastFilter(struct device *dev)
1210 {
1211 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1212 struct dev_mc_list *dmi=dev->mc_list;
1213 u_long iobase = dev->base_addr;
1214 int i;
1215 char *addrs, j, bit, byte;
1216 short *p = (short *) lp->mctbl;
1217 u16 hashcode;
1218 s32 crc, poly = CRC_POLYNOMIAL_LE;
1219
1220 while (set_bit(0, (void *)&lp->lock) != 0);
1221
1222 if (lp->shmem_length == IO_ONLY) {
1223 outb(0, EWRK3_IOPR);
1224 outw(EEPROM_OFFSET(lp->mctbl), EWRK3_PIR1);
1225 } else {
1226 outb(0, EWRK3_MPR);
1227 }
1228
1229 if (dev->flags & IFF_ALLMULTI) {
1230 for (i=0; i<(HASH_TABLE_LEN >> 3); i++) {
1231 if (lp->shmem_length == IO_ONLY) {
1232 outb(0xff, EWRK3_DATA);
1233 } else {
1234 writew(0xffff, p);
1235 p++; i++;
1236 }
1237 }
1238 } else {
1239
1240 if (lp->shmem_length == IO_ONLY) {
1241 for (i=0; i<(HASH_TABLE_LEN >> 4) - 1; i++) {
1242 outb(0x00, EWRK3_DATA);
1243 }
1244 outb(0x80, EWRK3_DATA); i++;
1245 for (; i<(HASH_TABLE_LEN >> 3); i++) {
1246 outb(0x00, EWRK3_DATA);
1247 }
1248 } else {
1249 memset_io(lp->mctbl, 0, (HASH_TABLE_LEN >> 3));
1250 writeb(0x80, (char *)(lp->mctbl + (HASH_TABLE_LEN >> 4) - 1));
1251 }
1252
1253
1254 for (i=0;i<dev->mc_count;i++) {
1255 addrs=dmi->dmi_addr;
1256 dmi=dmi->next;
1257 if ((*addrs & 0x01) == 1) {
1258 crc = 0xffffffff;
1259 for (byte=0;byte<ETH_ALEN;byte++) {
1260
1261 for (bit = *addrs++,j=0;j<8;j++, bit>>=1) {
1262 crc = (crc >> 1) ^ (((crc ^ bit) & 0x01) ? poly : 0);
1263 }
1264 }
1265 hashcode = crc & ((1 << 9) - 1);
1266
1267 byte = hashcode >> 3;
1268 bit = 1 << (hashcode & 0x07);
1269
1270 if (lp->shmem_length == IO_ONLY) {
1271 u_char tmp;
1272
1273 outw((short)((long)lp->mctbl) + byte, EWRK3_PIR1);
1274 tmp = inb(EWRK3_DATA);
1275 tmp |= bit;
1276 outw((short)((long)lp->mctbl) + byte, EWRK3_PIR1);
1277 outb(tmp, EWRK3_DATA);
1278 } else {
1279 writeb(readb(lp->mctbl + byte) | bit, lp->mctbl + byte);
1280 }
1281 }
1282 }
1283 }
1284
1285 lp->lock = 0;
1286
1287 return;
1288 }
1289
1290
1291
1292
1293 static void isa_probe(struct device *dev, u_long ioaddr)
1294 {
1295 int i = num_ewrk3s, maxSlots;
1296 u_long iobase;
1297
1298 if (!ioaddr && autoprobed) return ;
1299 if (ioaddr >= 0x400) return;
1300
1301 if (ioaddr == 0) {
1302 iobase = EWRK3_IO_BASE;
1303 maxSlots = 24;
1304 } else {
1305 iobase = ioaddr;
1306 maxSlots = i + 1;
1307 }
1308
1309 for (; (i<maxSlots) && (dev!=NULL);iobase+=EWRK3_IOP_INC, i++) {
1310 if (!check_region(iobase, EWRK3_TOTAL_SIZE)) {
1311 if (DevicePresent(iobase) == 0) {
1312 if ((dev = alloc_device(dev, iobase)) != NULL) {
1313 if (ewrk3_hw_init(dev, iobase) == 0) {
1314 num_ewrk3s++;
1315 }
1316 num_eth++;
1317 }
1318 }
1319 } else if (autoprobed) {
1320 printk("%s: region already allocated at 0x%04lx.\n", dev->name, iobase);
1321 }
1322 }
1323
1324 return;
1325 }
1326
1327
1328
1329
1330
1331 static void eisa_probe(struct device *dev, u_long ioaddr)
1332 {
1333 int i, maxSlots;
1334 u_long iobase;
1335 char name[EWRK3_STRLEN];
1336
1337 if (!ioaddr && autoprobed) return ;
1338 if (ioaddr < 0x1000) return;
1339
1340 if (ioaddr == 0) {
1341 iobase = EISA_SLOT_INC;
1342 i = 1;
1343 maxSlots = MAX_EISA_SLOTS;
1344 } else {
1345 iobase = ioaddr;
1346 i = (ioaddr >> 12);
1347 maxSlots = i + 1;
1348 }
1349
1350 for (i=1; (i<maxSlots) && (dev!=NULL); i++, iobase+=EISA_SLOT_INC) {
1351 if (EISA_signature(name, EISA_ID) == 0) {
1352 if (!check_region(iobase, EWRK3_TOTAL_SIZE)) {
1353 if (DevicePresent(iobase) == 0) {
1354 if ((dev = alloc_device(dev, iobase)) != NULL) {
1355 if (ewrk3_hw_init(dev, iobase) == 0) {
1356 num_ewrk3s++;
1357 }
1358 num_eth++;
1359 }
1360 }
1361 } else if (autoprobed) {
1362 printk("%s: region already allocated at 0x%04lx.\n", dev->name, iobase);
1363 }
1364 }
1365 }
1366
1367 return;
1368 }
1369
1370
1371
1372
1373
1374 static struct device *alloc_device(struct device *dev, u_long iobase)
1375 {
1376 int addAutoProbe = 0;
1377 struct device *tmp = NULL, *ret;
1378 int (*init)(struct device *) = NULL;
1379
1380
1381
1382
1383 if (!loading_module) {
1384 while (dev->next != NULL) {
1385 if ((dev->base_addr == EWRK3_NDA) || (dev->base_addr == 0)) break;
1386 dev = dev->next;
1387 num_eth++;
1388 }
1389
1390
1391
1392
1393
1394 if ((dev->base_addr == 0) && (num_ewrk3s > 0)) {
1395 addAutoProbe++;
1396 tmp = dev->next;
1397 init = dev->init;
1398 }
1399
1400
1401
1402
1403
1404 if ((dev->next == NULL) &&
1405 !((dev->base_addr == EWRK3_NDA) || (dev->base_addr == 0))){
1406 dev->next = (struct device *)kmalloc(sizeof(struct device) + 8,
1407 GFP_KERNEL);
1408
1409 dev = dev->next;
1410 if (dev == NULL) {
1411 printk("eth%d: Device not initialised, insufficient memory\n",
1412 num_eth);
1413 } else {
1414
1415
1416
1417
1418
1419 dev->name = (char *)(dev + 1);
1420 if (num_eth > 9999) {
1421 sprintf(dev->name,"eth????");
1422 } else {
1423 sprintf(dev->name,"eth%d", num_eth);
1424 }
1425 dev->base_addr = iobase;
1426 dev->next = NULL;
1427 dev->init = &ewrk3_probe;
1428 num_ewrk3s++;
1429 }
1430 }
1431 ret = dev;
1432
1433
1434
1435
1436
1437 if (ret != NULL) {
1438 if (addAutoProbe) {
1439 for (;(tmp->next!=NULL) && (tmp->base_addr!=EWRK3_NDA); tmp=tmp->next);
1440
1441
1442
1443
1444
1445 if ((tmp->next == NULL) && !(tmp->base_addr == EWRK3_NDA)) {
1446 tmp->next = (struct device *)kmalloc(sizeof(struct device) + 8,
1447 GFP_KERNEL);
1448 tmp = tmp->next;
1449 if (tmp == NULL) {
1450 printk("%s: Insufficient memory to extend the device list.\n",
1451 dev->name);
1452 } else {
1453
1454
1455
1456
1457
1458 tmp->name = (char *)(tmp + 1);
1459 if (num_eth > 9999) {
1460 sprintf(tmp->name,"eth????");
1461 } else {
1462 sprintf(tmp->name,"eth%d", num_eth);
1463 }
1464 tmp->base_addr = 0;
1465 tmp->next = NULL;
1466 tmp->init = init;
1467 }
1468 } else {
1469 tmp->base_addr = 0;
1470 }
1471 }
1472 }
1473 } else {
1474 ret = dev;
1475 }
1476
1477 return ret;
1478 }
1479
1480
1481
1482
1483 static int Read_EEPROM(u_long iobase, u_char eaddr)
1484 {
1485 int i;
1486
1487 outb((eaddr & 0x3f), EWRK3_PIR1);
1488 outb(EEPROM_RD, EWRK3_IOPR);
1489 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1490
1491 return inw(EWRK3_EPROM1);
1492 }
1493
1494
1495
1496
1497 static int Write_EEPROM(short data, u_long iobase, u_char eaddr)
1498 {
1499 int i;
1500
1501 outb(EEPROM_WR_EN, EWRK3_IOPR);
1502 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1503 outw(data, EWRK3_EPROM1);
1504 outb((eaddr & 0x3f), EWRK3_PIR1);
1505 outb(EEPROM_WR, EWRK3_IOPR);
1506 for (i=0;i<75000;i++) inb(EWRK3_CSR);
1507 outb(EEPROM_WR_DIS, EWRK3_IOPR);
1508 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1509
1510 return 0;
1511 }
1512
1513
1514
1515
1516 static void EthwrkSignature(char *name, char *eeprom_image)
1517 {
1518 u_long i,j,k;
1519 char *signatures[] = EWRK3_SIGNATURE;
1520
1521 strcpy(name, "");
1522 for (i=0;*signatures[i] != '\0' && *name == '\0';i++) {
1523 for (j=EEPROM_PNAME7,k=0;j<=EEPROM_PNAME0 && k<strlen(signatures[i]);j++) {
1524 if (signatures[i][k] == eeprom_image[j]) {
1525 k++;
1526 } else {
1527 k=0;
1528 }
1529 }
1530 if (k == strlen(signatures[i])) {
1531 for (k=0; k<EWRK3_STRLEN; k++) {
1532 name[k] = eeprom_image[EEPROM_PNAME7 + k];
1533 name[EWRK3_STRLEN] = '\0';
1534 }
1535 }
1536 }
1537
1538 return;
1539 }
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553 static int DevicePresent(u_long iobase)
1554 {
1555 union {
1556 struct {
1557 u32 a;
1558 u32 b;
1559 } llsig;
1560 char Sig[sizeof(u32) << 1];
1561 } dev;
1562 short sigLength;
1563 char data;
1564 int i, j, status = 0;
1565
1566 dev.llsig.a = ETH_PROM_SIG;
1567 dev.llsig.b = ETH_PROM_SIG;
1568 sigLength = sizeof(u32) << 1;
1569
1570 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
1571 data = inb(EWRK3_APROM);
1572 if (dev.Sig[j] == data) {
1573 j++;
1574 } else {
1575 if (data == dev.Sig[0]) {
1576 j=1;
1577 } else {
1578 j=0;
1579 }
1580 }
1581 }
1582
1583 if (j!=sigLength) {
1584 status = -ENODEV;
1585 }
1586
1587 return status;
1588 }
1589
1590 static u_char get_hw_addr(struct device *dev, u_char *eeprom_image, char chipType)
1591 {
1592 int i, j, k;
1593 u_short chksum;
1594 u_char crc, lfsr, sd, status = 0;
1595 u_long iobase = dev->base_addr;
1596 u16 tmp;
1597
1598 if (chipType == LeMAC2) {
1599 for (crc=0x6a, j=0; j<ETH_ALEN; j++) {
1600 sd = dev->dev_addr[j] = eeprom_image[EEPROM_PADDR0 + j];
1601 outb(dev->dev_addr[j], EWRK3_PAR0 + j);
1602 for (k=0; k<8; k++, sd >>= 1) {
1603 lfsr = ((((crc & 0x02) >> 1) ^ (crc & 0x01)) ^ (sd & 0x01)) << 7;
1604 crc = (crc >> 1) + lfsr;
1605 }
1606 }
1607 if (crc != eeprom_image[EEPROM_PA_CRC]) status = -1;
1608 } else {
1609 for (i=0,k=0;i<ETH_ALEN;) {
1610 k <<= 1 ;
1611 if (k > 0xffff) k-=0xffff;
1612
1613 k += (u_char) (tmp = inb(EWRK3_APROM));
1614 dev->dev_addr[i] = (u_char) tmp;
1615 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
1616 i++;
1617 k += (u_short) ((tmp = inb(EWRK3_APROM)) << 8);
1618 dev->dev_addr[i] = (u_char) tmp;
1619 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
1620 i++;
1621
1622 if (k > 0xffff) k-=0xffff;
1623 }
1624 if (k == 0xffff) k=0;
1625 chksum = inb(EWRK3_APROM);
1626 chksum |= (inb(EWRK3_APROM)<<8);
1627 if (k != chksum) status = -1;
1628 }
1629
1630 return status;
1631 }
1632
1633
1634
1635
1636 static int EISA_signature(char *name, s32 eisa_id)
1637 {
1638 u_long i;
1639 char *signatures[] = EWRK3_SIGNATURE;
1640 char ManCode[EWRK3_STRLEN];
1641 union {
1642 s32 ID;
1643 char Id[4];
1644 } Eisa;
1645 int status = 0;
1646
1647 *name = '\0';
1648 for (i=0; i<4; i++) {
1649 Eisa.Id[i] = inb(eisa_id + i);
1650 }
1651
1652 ManCode[0]=(((Eisa.Id[0]>>2)&0x1f)+0x40);
1653 ManCode[1]=(((Eisa.Id[1]&0xe0)>>5)+((Eisa.Id[0]&0x03)<<3)+0x40);
1654 ManCode[2]=(((Eisa.Id[2]>>4)&0x0f)+0x30);
1655 ManCode[3]=((Eisa.Id[2]&0x0f)+0x30);
1656 ManCode[4]=(((Eisa.Id[3]>>4)&0x0f)+0x30);
1657 ManCode[5]='\0';
1658
1659 for (i=0;(*signatures[i] != '\0') && (*name == '\0');i++) {
1660 if (strstr(ManCode, signatures[i]) != NULL) {
1661 strcpy(name,ManCode);
1662 status = 1;
1663 }
1664 }
1665
1666 return status;
1667 }
1668
1669
1670
1671
1672
1673 static int ewrk3_ioctl(struct device *dev, struct ifreq *rq, int cmd)
1674 {
1675 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1676 struct ewrk3_ioctl *ioc = (struct ewrk3_ioctl *) &rq->ifr_data;
1677 u_long iobase = dev->base_addr;
1678 int i, j, status = 0;
1679 u_char csr;
1680 union {
1681 u_char addr[HASH_TABLE_LEN * ETH_ALEN];
1682 u_short val[(HASH_TABLE_LEN * ETH_ALEN) >> 1];
1683 } tmp;
1684
1685 switch(ioc->cmd) {
1686 case EWRK3_GET_HWADDR:
1687 for (i=0; i<ETH_ALEN; i++) {
1688 tmp.addr[i] = dev->dev_addr[i];
1689 }
1690 ioc->len = ETH_ALEN;
1691 if (!(status = verify_area(VERIFY_WRITE, (void *)ioc->data, ioc->len))) {
1692 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1693 }
1694
1695 break;
1696 case EWRK3_SET_HWADDR:
1697 if (suser()) {
1698 if (!(status = verify_area(VERIFY_READ, (void *)ioc->data, ETH_ALEN))) {
1699 csr = inb(EWRK3_CSR);
1700 csr |= (CSR_TXD|CSR_RXD);
1701 outb(csr, EWRK3_CSR);
1702
1703 memcpy_fromfs(tmp.addr,ioc->data,ETH_ALEN);
1704 for (i=0; i<ETH_ALEN; i++) {
1705 dev->dev_addr[i] = tmp.addr[i];
1706 outb(tmp.addr[i], EWRK3_PAR0 + i);
1707 }
1708
1709 csr &= ~(CSR_TXD|CSR_RXD);
1710 outb(csr, EWRK3_CSR);
1711 }
1712 } else {
1713 status = -EPERM;
1714 }
1715
1716 break;
1717 case EWRK3_SET_PROM:
1718 if (suser()) {
1719 csr = inb(EWRK3_CSR);
1720 csr |= CSR_PME;
1721 csr &= ~CSR_MCE;
1722 outb(csr, EWRK3_CSR);
1723 } else {
1724 status = -EPERM;
1725 }
1726
1727 break;
1728 case EWRK3_CLR_PROM:
1729 if (suser()) {
1730 csr = inb(EWRK3_CSR);
1731 csr &= ~CSR_PME;
1732 outb(csr, EWRK3_CSR);
1733 } else {
1734 status = -EPERM;
1735 }
1736
1737 break;
1738 case EWRK3_SAY_BOO:
1739 printk("%s: Boo!\n", dev->name);
1740
1741 break;
1742 case EWRK3_GET_MCA:
1743 if (!(status = verify_area(VERIFY_WRITE, ioc->data, ioc->len))) {
1744 while (set_bit(0, (void *)&lp->lock) != 0);
1745 if (lp->shmem_length == IO_ONLY) {
1746 outb(0, EWRK3_IOPR);
1747 outw(PAGE0_HTE, EWRK3_PIR1);
1748 for (i=0; i<(HASH_TABLE_LEN >> 3); i++) {
1749 tmp.addr[i] = inb(EWRK3_DATA);
1750 }
1751 } else {
1752 outb(0, EWRK3_MPR);
1753 memcpy_fromio(tmp.addr, (char *)(lp->shmem_base + PAGE0_HTE), (HASH_TABLE_LEN >> 3));
1754 }
1755 ioc->len = (HASH_TABLE_LEN >> 3);
1756 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1757 }
1758 lp->lock = 0;
1759
1760 break;
1761 case EWRK3_SET_MCA:
1762 if (suser()) {
1763 if (!(status=verify_area(VERIFY_READ, ioc->data, ETH_ALEN*ioc->len))) {
1764 memcpy_fromfs(tmp.addr, ioc->data, ETH_ALEN * ioc->len);
1765 set_multicast_list(dev);
1766 }
1767 } else {
1768 status = -EPERM;
1769 }
1770
1771 break;
1772 case EWRK3_CLR_MCA:
1773 if (suser()) {
1774 set_multicast_list(dev);
1775 } else {
1776 status = -EPERM;
1777 }
1778
1779 break;
1780 case EWRK3_MCA_EN:
1781 if (suser()) {
1782 csr = inb(EWRK3_CSR);
1783 csr |= CSR_MCE;
1784 csr &= ~CSR_PME;
1785 outb(csr, EWRK3_CSR);
1786 } else {
1787 status = -EPERM;
1788 }
1789
1790 break;
1791 case EWRK3_GET_STATS:
1792 cli();
1793 ioc->len = sizeof(lp->pktStats);
1794 if (!(status=verify_area(VERIFY_WRITE, ioc->data, ioc->len))) {
1795 memcpy_tofs(ioc->data, &lp->pktStats, ioc->len);
1796 }
1797 sti();
1798
1799 break;
1800 case EWRK3_CLR_STATS:
1801 if (suser()) {
1802 cli();
1803 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
1804 sti();
1805 } else {
1806 status = -EPERM;
1807 }
1808
1809 break;
1810 case EWRK3_GET_CSR:
1811 tmp.addr[0] = inb(EWRK3_CSR);
1812 ioc->len = 1;
1813 if (!(status=verify_area(VERIFY_WRITE, ioc->data, ioc->len))) {
1814 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1815 }
1816
1817 break;
1818 case EWRK3_SET_CSR:
1819 if (suser()) {
1820 if (!(status=verify_area(VERIFY_READ, ioc->data, 1))) {
1821 memcpy_fromfs(tmp.addr, ioc->data, 1);
1822 outb(tmp.addr[0], EWRK3_CSR);
1823 }
1824 } else {
1825 status = -EPERM;
1826 }
1827
1828 break;
1829 case EWRK3_GET_EEPROM:
1830 if (suser()) {
1831 for (i=0; i<(EEPROM_MAX>>1); i++) {
1832 tmp.val[i] = (short)Read_EEPROM(iobase, i);
1833 }
1834 i = EEPROM_MAX;
1835 tmp.addr[i++] = inb(EWRK3_CMR);
1836 for (j=0;j<ETH_ALEN;j++) {
1837 tmp.addr[i++] = inb(EWRK3_PAR0 + j);
1838 }
1839 ioc->len = EEPROM_MAX + 1 + ETH_ALEN;
1840 if (!(status=verify_area(VERIFY_WRITE, ioc->data, ioc->len))) {
1841 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1842 }
1843 } else {
1844 status = -EPERM;
1845 }
1846
1847 break;
1848 case EWRK3_SET_EEPROM:
1849 if (suser()) {
1850 if (!(status=verify_area(VERIFY_READ, ioc->data, EEPROM_MAX))) {
1851 memcpy_fromfs(tmp.addr, ioc->data, EEPROM_MAX);
1852 for (i=0; i<(EEPROM_MAX>>1); i++) {
1853 Write_EEPROM(tmp.val[i], iobase, i);
1854 }
1855 }
1856 } else {
1857 status = -EPERM;
1858 }
1859
1860 break;
1861 case EWRK3_GET_CMR:
1862 tmp.addr[0] = inb(EWRK3_CMR);
1863 ioc->len = 1;
1864 if (!(status=verify_area(VERIFY_WRITE, ioc->data, ioc->len))) {
1865 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1866 }
1867
1868 break;
1869 case EWRK3_SET_TX_CUT_THRU:
1870 if (suser()) {
1871 lp->txc = 1;
1872 } else {
1873 status = -EPERM;
1874 }
1875
1876 break;
1877 case EWRK3_CLR_TX_CUT_THRU:
1878 if (suser()) {
1879 lp->txc = 0;
1880 } else {
1881 status = -EPERM;
1882 }
1883
1884 break;
1885 default:
1886 status = -EOPNOTSUPP;
1887 }
1888
1889 return status;
1890 }
1891
1892 #ifdef MODULE
1893 static char devicename[9] = { 0, };
1894 static struct device thisEthwrk = {
1895 devicename,
1896 0, 0, 0, 0,
1897 0x300, 5,
1898 0, 0, 0, NULL, ewrk3_probe };
1899
1900 static int io=0x300;
1901 static int irq=5;
1902
1903 int
1904 init_module(void)
1905 {
1906 thisEthwrk.base_addr=io;
1907 thisEthwrk.irq=irq;
1908 if (register_netdev(&thisEthwrk) != 0)
1909 return -EIO;
1910 return 0;
1911 }
1912
1913 void
1914 cleanup_module(void)
1915 {
1916 if (thisEthwrk.priv) {
1917 kfree(thisEthwrk.priv);
1918 thisEthwrk.priv = NULL;
1919 }
1920 thisEthwrk.irq = 0;
1921
1922 unregister_netdev(&thisEthwrk);
1923 release_region(thisEthwrk.base_addr, EWRK3_TOTAL_SIZE);
1924 }
1925 #endif
1926
1927
1928
1929
1930
1931
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1935